MH4S64CBMD-10 データシートの表示（PDF） - MITSUBISHI ELECTRIC
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MH4S64CBMD-10 Datasheet PDF : 47 Pages
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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH4S64CBMD-10,-12,-15,-10B,-12B,-15B
268435456-BIT (4194304-WORD BY 64-BIT)SynchronousDRAM
Serial Presence Detect Table
Byte
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Function described
SPD enrty data
Defines # bytes written into serial memory at module mfgr
128
Total # bytes of SPD memory device
256 Bytes
Fundamental memory type
SDRAM
# Row Addresses on this assembly
A0-A10
# Column Addresses on this assembly
A0-A8
# Module Banks on this assembly
2BANK
Data Width of this assembly...
x64
... Data Width continuation
0
Voltage interface standard of this assembly
LVTTL
SDRAM Cycletime at Max. Supported CAS Latency (CL). -10
10ns
Cycle time for CL=3
-12
12ns
-15
15ns
SDRAM Access from Clock
-10
8ns
tAC for CL=3
-12
8ns
-15
9ns
DIMM Configuration type (Non-parity,Parity,ECC)
Non-PARITY
Refresh Rate/Type
self refresh(15.625uS)
SDRAM width,Primary DRAM
x8
Error Checking SDRAM data width
n/a
Minimum Clock Delay,Back to Back Random Column Addresses
1
Burst Lengths Supported
1/2/4/8
# Banks on Each SDRAM device
2bank
CAS# Latency
CL=1/2/3
CS# Latency
0
Write Latency
0
SDRAM Module Attributes
non-buffered,non-registered
SDRAM Device Attributes:General
Precharge All,Auto precharge
SDRAM Cycle time(2nd highest CAS latency)
-10
15ns
Cycle time for CL=2
-12
15ns
-15
20ns
SDRAM Access form Clock(2nd highest CAS latency) -10
9ns
tAC for CL=2
-12
9.5ns
-15
12ns
SDRAM Cycle time(3rd highest CAS latency)
-10
30ns
Cycle time for CL=1
-12
30ns
-15
30ns
SDRAM Access form Clock(3rd highest CAS latency) -10
27ns
tAC for CL=1
-12
27ns
-15
30ns
Precharge to Active Minimum
-10
30ns
-12
30ns
-15
40ns
Row Active to Row Active Min.
-10
20ns
-12
24ns
-15
30ns
SPD DATA(hex)
80
08
04
0B
09
02
40
00
01
A0
C0
F0
80
80
90
00
80
08
00
01
0F
02
06
01
01
00
06
F0
F0
FF
90
95
C0
78
78
78
6C
6C
78
1E
1E
28
14
18
1E
MIT-DS-0113-1.1
MITSUBISHI
ELECTRIC
( 4 / 47 )
25.Mar..1997
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