
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
USING INTELLIGENT POWER MODULES
Figure 6.37 Interface Circuit Layout Example for Dual IPMs
UP
FO
-+
SHIELD GROUND TO VUPC
UN
U
FO
-+
SHIELD GROUND TO VUNC
SHIELD GROUND TO VVPC
VP
FO
-+
VN
FO
V
-+
SHIELD GROUND TO VVNC
SHIELD GROUND TO VWPC
WP
FO
-+
WN
FO
DIGITAL
GROUND
MID-LAYER
SHIELD
UP
VP
WP
UN VN WN
TO
CONTROL
POWER
SOURCE
W
-+
SHIELD GROUND TO VWNC
SHIELDS GROUND
TO NEGATIVE SIDE
OF EACH CONTROL
POWER SUPPLY
LEGEND
TOP LAYER
MIDDLE LAYER
BOTTOM LAYER
Sep.1998