IS61LPS25636D-200B(2002) データシートの表示（PDF） - Integrated Silicon Solution

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IS61LPS25636D-200B
(Rev.:2002)

256K x 32, 256K x 36, 512K x 18 SYNCHRONOUS PIPELINED, SINGLE-CYCLE DESELECT STATIC RAM

Integrated Silicon Solution 

IS61LPS25632T/D/J, IS61LPS25636T/D/J, IS61LPS51218T/D/J

CAPACITANCE(1,2)

Symbol Parameter

Conditions

Max.

Unit

CIN

Input Capacitance

VIN = 0V

6

pF

COUT

Input/Output Capacitance

VOUT = 0V

8

pF

Notes:

1. Tested initially and after any design or process changes that may affect these parameters.

2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.

®

ISSI

3.3V I/O AC TEST CONDITIONS

Parameter

Input Pulse Level

Input Rise and Fall Times

Input and Output Timing

and Reference Level

Output Load

Unit

0V to 3.0V

1ns

1.5V

See Figures 1 and 2

3.3V I/O OUTPUT LOAD EQUIVALENT

OUTPUT

ZO = 50Ω

50Ω

1.5V

Figure 1

+3.3V

317 Ω

OUTPUT

351 Ω

Figure 2

5 pF

Including

jig and

scope

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

13

PRELIMINARYINFORMATION Rev. 00B

04/29/02

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