ADT7490
1
9
1
9
SCL
SDA
0
START BY
MASTER
1
0
1
1
1
0
FRAME 1
SERIAL BUS ADDRESS BYTE
R/W
D7
ACK. BY
ADT7490
1
SCL (CONTINUED)
D6 D5 D4 D3 D2 D1 D0
FRAME 2
ADDRESS POINTER REGISTER BYTE
ACK. BY
ADT7490
9
SDA (CONTINUED)
D7 D6 D5 D4 D3 D2 D1 D0
FRAME 3
DATA BYTE
ACK. BY STOP BY
ADT7490 MASTER
Figure 19. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
1
9
1
9
SCL
SDA
0
START BY
MASTER
1
0
1
1
1
0 R/W
D7 D6 D5 D4 D3 D2 D1 D0
FRAME 1
SERIAL BUS ADDRESS BYTE
ACK. BY
ADT7490
FRAME 2
ADDRESS POINTER REGISTER BYTE
ACK. BY STOP BY
ADT7490 MASTER
Figure 20. Writing to the Address Pointer Register Only
1
9
1
9
SCL
SDA
0
START BY
MASTER
1
0
1
1
1
0 R/W
D7 D6 D5 D4 D3 D2 D1
FRAME 1
SERIAL BUS ADDRESS BYTE
ACK. BY
ADT7490
FRAME 2
DATA BYTE FROM ADT7490
Figure 21. Reading Data from a Previously Selected Register
D0
NO ACK. BY STOP BY
MASTER MASTER
It is possible to read a data byte from a data register without
first writing to the address pointer register if the address pointer
register is already at the correct value. However, it is not possi-
ble to write data to a register without writing to the address
pointer register because the first data byte of a write is always
written to the address pointer register.
In addition to supporting the send byte and receive byte
protocols, the ADT7490 also supports the read byte protocol
(see System Management Bus Specifications Rev. 2 for more
information; this document is available from the SMBus
organization).
If several read or write operations must be performed in succes-
sion, the master can send a repeat start condition instead of a
stop condition to begin a new operation.
WRITE OPERATIONS
The SMBus specification defines several protocols for different
types of read and write operations. The ones used in the
ADT7490 are discussed here. The following abbreviations are
used in the diagrams:
• S: Start
• P: Stop
• R: Read
• W: Write
• A: Acknowledge
• A: No acknowledge
The ADT7490 uses the following SMBus write protocols.
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