ADSP-21366(RevA) データシートの表示（PDF） - Analog Devices

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ADSP-21366
(Rev.:RevA)

SHARC® Processor

Analog Devices 

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Timer WDTH_CAP Timing

The following timing specification applies to Timer0, Timer1,

and Timer2 in WDTH_CAP (pulse width count and capture)

mode. Timer signals are routed to the DAI_P20–1 pins through

the SRU. Therefore, the timing specification provided below are

valid at the DAI_P20–1 pins.

Table 18. Timer Width Capture Timing

Parameter

Timing Requirement

tPWI

Timer Pulse Width

Min

2 tPCLK

Max

2(231– 1) tPCLK

Unit

ns

tPWI

DAI_P20-1

(TIMER2-0)

Figure 14. Timer Width Capture Timing

DAI Pin to Pin Direct Routing

For direct pin connections only (for example, DAI_PB01_I to

DAI_PB02_O).

Table 19. DAI Pin to Pin Routing

Parameter

Timing Requirement

tDPIO

Delay DAI Pin Input Valid to DAI Output Valid

Min

Max

Unit

1.5

10

ns

DAI_Pn

DAI_Pm

tDPIO

Figure 15. DAI Pin to Pin Direct Routing

Rev. A | Page 23 of 52 | December 2006

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