ADSP-21267 データシートの表示（PDF） - Analog Devices

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ADSP-21267

SHARC® Processor

Analog Devices 

ADSP-21267

PRELIMINARY TECHNICAL DATA

KEY FEATURES

At 150 MHz (6.65 ns) core instruction rate, the ADSP-21267

operates at 900 MFLOPS performance whether operating

on fixed or floating point data

300 MMACS sustained performance at 150 MHz

Code compatibility—At assembly level, uses the same

instruction set as other SHARC DSPs

Super Harvard Architecture—three independent buses for

dual data fetch, instruction fetch, and nonintrusive, zero-

overhead I/O

1M Bit on-chip dual-ported SRAM (0.5M Bit in block 0 and

0.5M Bit in block 1) for simultaneous access by core proces-

sor and DMA

3M Bits on-chip dual-ported mask-programmable ROM (1.5M

Bits in block 0 and 1.5M Bits in block 1)

Dual Data Address Generators (DAGs) with modulo and bit-

reverse addressing

Zero-overhead looping with single-cycle loop setup, provid-

ing efficient program sequencing

Single Instruction Multiple Data (SIMD) architecture

provides:

Two computational processing elements

Concurrent execution— Each processing element executes

the same instruction, but operates on different data

DMA Controller supports:

18 zero-overhead DMA channels for transfers between

ADSP-21267 internal memory and the four serial ports,

the input data port (IDP) , SPI-compatible port, and the

parallel port

32-bit background DMA transfers at core clock speed, in

parallel with full-speed processor execution

Asynchronous parallel/external port provides:

Access to asynchronous external memory

16 multiplexed address/data lines that can support 24-bit

address external address range with 8-bit data or 16-bit

address external address range with 16-bit data

50 Mbyte per sec transfer rate

256 word page boundaries

External memory access in a dedicated DMA channel

8- to 32- bit and 16- to 32-bit word packing options

Programmable wait state options: 2 to 31 CCLK

Digital Audio Interface (DAI) includes four serial ports, two

precision clock generators, an input data port/parallel data

acquisition port, three timers and a signal routing unit

Serial Ports provide:

Four dual data line serial ports that operate at 37.5M Bits/s

on each data line —each has a clock, frame sync and two

data lines that can be configured as either a receiver or

transmitter pair

Left-justified Sample Pair and I2S Support, programmable

direction for up to 16 simultaneous receive or transmit

channels using two I2S compatible stereo devices per

serial port

TDM support for telecommunications interfaces including

128 TDM channel support for newer telephony inter-

faces such as H.100/H.110

Up to 4 full-duplex TDM streams, each with 128 channels

per frame

Companding selection on a per channel basis in TDM mode

Input Data Port provides an additional input path to the DSP

core configurable as either eight channels of I2S or serial

data or as seven channels plus a single 20-bit wide syn-

chronous parallel data acquisition port

Supports receive audio channel data in I2S, Left-justified

sample pair, or right-justified mode

Signal Routing Unit (SRU) provides configurable and flexible

connections between all DAI components, four serial

ports, three timers, 10 interrupts, six flag inputs, six flag

outputs, two precision clock generators, an input data

port/parallel data acquisition port, and 20 SRU I/O pins

(DAI_Px)

Serial Peripheral Interface (SPI)

Master or slave serial boot through SPI

Full-duplex operation

Master-Slave mode multi-master support

Open drain outputs

Programmable baud rates, clock polarities and phases

3 Muxed Flag/IRQ lines

1 Muxed Flag/Timer expired line

ROM Based Security features:

JTAG access to memory permitted with a 64-bit key

Protected memory regions that can be assigned to limit

access under program control to sensitive code

PLL has a wide variety of software and hardware multi-

plier/divider ratios

JTAG background telemetry for enhanced emulation

features

IEEE 1149.1 JTAG standard test access port and on-chip

emulation

Dual voltage: 3.3 V I/O, 1.2 V core

Available in 136-ball BGA and 144-lead LQFP packages

Also available in lead-free packages

Rev. PrA | Page 2 of 44 | January 2004

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