ADSP-21266 データシートの表示（PDF） - Analog Devices

部品番号

コンポーネント説明

メーカー

ADSP-21266

SHARC Embedded Processor

Analog Devices 

ADSP-21261/ADSP-21262/ADSP-21266

JTAG Test Access Port and Emulation

Table 37. JTAG Test Access Port and Emulation

Parameter

Timing Requirements

tTCK

tSTAP

tHTAP

tSSYS

tHSYS

tTRSTW

TCK Period

TDI, TMS Setup Before TCK High

TDI, TMS Hold After TCK High

System Inputs Setup Before TCK High1

System Inputs Hold After TCK High1

TRST Pulse Width

Min

20

5

6

7

8

4 × tCK

Switching Characteristics

tDTDO

tDSYS

TDO Delay from TCK Low

System Outputs Delay After TCK Low2

1 System Inputs = AD15–0, SPIDS, CLK_CFG1–0, RESET, BOOT_CFG1–0, MISO, MOSI, SPICLK, DAI_Px, FLAG3–0.

2 System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, CLKOUT, EMU, ALE.

Max

7

10

Unit

ns

ns

ns

ns

ns

ns

ns

ns

TCK

TMS

TDI

TDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS

tTCK

tDTDO

tSTAP

tSSYS

tDSYS

tHTAP

tHSYS

Figure 27. JTAG Test Access Port and Emulation

Rev. G | Page 36 of 48 | December 2012

Share Link: