ADSP-21266 データシートの表示（PDF） - Analog Devices

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ADSP-21266

SHARC Embedded Processor

Analog Devices 

ADSP-21261/ADSP-21262/ADSP-21266

SPI Interface Protocol—Master

Table 35. SPI Interface Protocol—Master

Parameter

Timing Requirements

tSSPIDM

tHSPIDM

Data Input Valid to SPICLK Edge (Data Input Setup Time)

SPICLK Last Sampling Edge to Data Input Not Valid

Switching Characteristics

tSPICLKM

tSPICHM

tSPICLM

tDDSPIDM

tHDSPIDM

tSDSCIM

tHDSM

tSPITDM

Serial Clock Cycle

Serial Clock High Period

Serial Clock Low Period

SPICLK Edge to Data Out Valid (Data Out Delay Time)

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

FLAG3–0 OUT (SPI Device Select) Low to First SPICLK Edge

Last SPICLK Edge to FLAG3–0 OUT High

Sequential Transfer Delay

Min

5

2

8 × tCCLK

4 × tCCLK – 2

4 × tCCLK – 2

10

4 × tCCLK – 2

4 × tCCLK – 1

4 × tCCLK – 1

Max

3

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

DPI

(OUTPUT)

SPICLK

(CP = 0,

CP = 1)

(OUTPUT)

MOSI

(OUTPUT)

CPHASE = 1

MISO

(INPUT)

tSDSCIM

tSPICHM

tSPICLM

tDDSPIDM

tSSPIDM

tHSPIDM

MOSI

(OUTPUT)

CPHASE = 0

tSSPIDM

MISO

(INPUT)

tHSPIDM

tDDSPIDM

tSPICLKM

tHDSPIDM

tHDSM

tSPITDM

tSSPIDM

tHSPIDM

tHDSPIDM

Figure 25. SPI Interface Protocol—Master

Rev. G | Page 34 of 48 | December 2012

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