ADP3168 データシートの表示（PDF） - Analog Devices
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ADP3168 Datasheet PDF : 24 Pages
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ADP3168
The latch-off function can be reset either by removing and
reapplying VCC to the ADP3168, or by pulling the EN pin low
for a short time. To disable the short-circuit latch-off function,
the external resistor to ground should be left open, and a high
value (>1 MΩ) resistor should be connected from DELAY to
VCC. This prevents the DELAY capacitor from discharging, so
the 1.8 V threshold is never reached. The resistor has an impact
on the soft-start time because the current through it adds to the
internal 20 µA current source.
Figure 8. Start-Up Waveforms, Circuit of Figure 12. Channel 1—PWRGD,
Channel 2—VOUT, Channel 3—High-Side MOSFET VGS,
Channel 4—Low-Side MOSFET VGS
CURRENT-LIMIT, SHORT-CIRCUIT, AND
LATCH-OFF PROTECTION
The ADP3168 compares a programmable current-limit set
point to the voltage from the output of the current-sense
amplifier. The level of current limit is set with the resistor from
the ILIMIT pin to ground. During normal operation, the
voltage on ILIMIT is 3 V. The current through the external
resistor is internally scaled to give a current-limit threshold of
10.4 mV/µA. If the difference in voltage between CSREF and
CSCOMP rises above the current-limit threshold, the internal
current-limit amplifier controls the internal COMP voltage to
maintain the average output current at the limit.
After the limit is reached, the 3 V pull-up on the DELAY pin is
disconnected, and the external delay capacitor is discharged
through the external resistor. A comparator monitors the
DELAY voltage and shuts off the controller when the voltage
drops below 1.8 V. The current-limit latch-off delay time is
therefore set by the RC time constant discharging from 3 V to
1.8 V. The Application Information section discusses the
selection of CDLY and RDLY.
Because the controller continues to cycle the phases during the
latch-off delay time, if the short is removed before the 1.8 V
threshold is reached, the controller returns to normal operation.
The recovery characteristic depends on the state of PWRGD. If
the output voltage is within the PWRGD window, the controller
resumes normal operation. However, if a short circuit has
caused the output voltage to drop below the PWRGD threshold,
a soft-start cycle is initiated.
Figure 9. Overcurrent Latch-Off Waveforms, Circuit of Figure 11. Channel 1—
PWRGD, Channel 2—VOUT, Channel 3—CSCOMP Pin of ADP3168,
Channel 4—High-Side MOSFET VGS
During startup, when the output voltage is below 200 mV, a
secondary current limit is active. This is necessary because the
voltage swing of CSCOMP cannot go below ground. This
secondary current limit controls the internal COMP voltage
to the PWM comparators to 2 V. This limits the voltage drop
across the low-side MOSFETs through the current-balance
circuitry.
There is also an inherent per-phase current limit that protects
individual phases in the case where one or more phases stop
functioning because of a faulty component. This limit is based
on the maximum normal mode COMP voltage.
Rev. B | Page 11 of 24
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