ADN4662 データシートの表示（PDF） - Analog Devices

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ADN4662

Single, 3 V, CMOS, LVDS Differential Line Receiver

Analog Devices 

Data Sheet

Test Circuits and Timing Diagrams

SIGNAL

GENERATOR

VCC

RIN+

RIN–

50Ω 50Ω

ROUT

CL

CL = LOAD AND TEST JIG CAPACITANCE

Figure 2. Test Circuit for Receiver Propagation Delay and Transition Time

RIN–

RIN+

0V (DIFFERENTIAL)

tPLHD

VID = 200mV

1.2V

tPHLD

80%

80%

1.3V

1.1V

VOH

ROUT

1.5V

1.5V

20%

20%

tTLH

tTHL

VOL

Figure 3. Receiver Propagation Delay and Transition Time Waveforms

ADN4662

Rev. A | Page 5 of 12

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