ADN2806ACPZ-500RL7 データシートの表示（PDF） - Analog Devices

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ADN2806ACPZ-500RL7

622 Mbps Clock and Data Recovery IC

Analog Devices 

ADN2806

At medium jitter frequencies, the gain and tuning range of the

VCO are not large enough to track input jitter. In this case, the

VCO control voltage becomes large and saturates, and the VCO

frequency dwells at one extreme of its tuning range. The size of

the VCO tuning range, therefore, has only a small effect on the

jitter accommodation. The delay-locked loop control voltage is

now larger; therefore, the phase shifter takes on the burden of

tracking the input jitter. The phase shifter range, in UI, can be

seen as a broad plateau on the jitter tolerance curve. The phase

shifter has a minimum range of 2 UI at all data rates.

The gain of the loop integrator is small for high jitter

frequencies; therefore, larger phase differences are needed to

increase the loop control voltage enough to tune the range of

the phase shifter. However, large phase errors at high jitter

frequencies cannot be tolerated. In this region, the gain of the

integrator determines the jitter accommodation. Because the

gain of the loop integrator declines linearly with frequency,

jitter accommodation is lower with higher jitter frequency. At

the highest frequencies, the loop gain is very small, and little

tuning of the phase shifter can be expected. In this case, jitter

accommodation is determined by the eye opening of the input

data, the static phase error, and the residual loop jitter

generation. The jitter accommodation is roughly 0.5 UI in this

region. The corner frequency between the declining slope and

the flat region is the closed-loop bandwidth of the delay-locked

loop, which is roughly 1.0 MHz at 622 Mbps.

Rev. C | Page 12 of 20

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