ADM1191(RevB) データシートの表示（PDF） - Analog Devices

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ADM1191
(Rev.:RevB)

Digital Power Monitor with Convert Pin and ALERTB Output

Analog Devices 

ADM1191

Base Address

A1 Pin State

Floating

Floating

High

High

High

High

1 X = don’t care.

A0 Pin State

Floating

High

Ground

Resistor to ground

Floating

High

A1 Pin Logic State

10

10

11

11

11

11

A0 Pin Logic State

10

11

00

01

10

11

Address in Binary1

0111010X

0111011X

0111100X

0111101X

0111110X

0111111X

Address in Hex

0x74

0x76

0x78

0x7A

0x7C

0x7E

1

91

9

SCL

SDA

0

1

START BY MASTER

1

SCL

(CONTINUED)

1 A1A A1B A0A A0B R/W

D7 D6 D5 D4 D3 D2 D1 D0

FRAME 1

SLAVE ADDRESS

ACKNOWLEDGE BY

SLAVE

FRAME 2

COMMAND CODE

ACKNOWLEDGE BY

SLAVE

9

1

9

SDA

(CONTINUED)

D7 D6 D5 D4 D3 D2 D1 D0

FRAME 3

DATA BYTE

ACKNOWLEDGE BY

SLAVE

D7 D6 D5 D4 D3 D2 D1 D0

FRAME N

DATA BYTE

ACKNOWLEDGE BY

SLAVE

STOP

BY

MASTER

Figure 16. General I2C Write Timing Diagram

1

91

9

SCL

SDA

0

1

START BY MASTER

1

SCL

(CONTINUED)

1 A1A A1B A0A A0B R/W

D7 D6 D5 D4 D3 D2 D1 D0

FRAME 1

SLAVE ADDRESS

ACKNOWLEDGE BY

SLAVE

FRAME 2

DATA BYTE

ACKNOWLEDGE BY

MASTER

9

1

9

SDA

(CONTINUED)

D7 D6 D5 D4 D3 D2 D1 D0

FRAME 3

DATA BYTE

ACKNOWLEDGE BY

MASTER

D7 D6 D5 D4 D3 D2 D1 D0

FRAME N

DATA BYTE

NO ACKNOWLEDGE

STOP

BY

MASTER

Figure 17. General I2C Read Timing Diagram

SCL

tLOW

tR

tHD;STA

tHD;DAT

SDA

tBUF

P

S

tF

tHIGH

tSU;DAT

tHD;STA

tSU;STA

S

Figure 18. Serial Bus Timing Diagram

tSU;STO

P

Rev. B | Page 10 of 16

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