AD9847AKST データシートの表示（PDF） - Analog Devices

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AD9847AKST

10-Bit 40 MSPS CCD Signal Processor with Integrated Timing Driver

Analog Devices 

AD9847

Address

Bit

Content

Width

AFE Register Breakdown

oprmode [7:0]

[1:0]

2'h0

2'h1

2'h2

2'h3

[2]

[3]

[4]

[5]

[6]

[7]

Default

Value

8'h0

Register Name Register Description

powerdown[1:0]

disblack

test mode

test mode

test mode

test mode

test mode

Serial Address:

8'h00 {oprmode[5:0]}, 8'h01 {oprmode[7:6]}

Full Power

Fast Recovery

Reference Standby

Total Shutdown

Disable Black Loop Clamping (High Active)

Test Mode—Should Be Set Low

Test Mode—Should Be Set High

Test Mode—Should Be Set Low

Test Mode—Should Be Set Low

Test Mode—Should Be Set Low

ctlmode

[5:0]

[2:0]

[3]

[4]

[5]

6'h0

3'h0

3'h1

3'h2

3'h3

3'h4

3'h5

3'h6

3'h7

1'h0

1'h1

1'h0

1'h1

ctlmode[2:0]

enablepxga

outputlat

tristateout

Serial Address: 8'h06 {cltmode[5:0]}

Off

Mosaic Separate

VD Selected/Mosaic Interlaced

Mosaic Repeat

Three-Color

Three-Color II

Four-Color

Four-Color II

Enable PxGA (High Active)

Latch Output Data on Selected DOUT Edge

Leave Output Latch Transparent

ADC Outputs Are Driven

ADC Outputs Are Three-Stated

PRECISION TIMING HIGH SPEED TIMING

GENERATION

The AD9847 generates flexible high speed timing signals using

the Precision Timing core. This core is the foundation for generating

the timing used for both the CCD and the AFE, the reset gate RG,

horizontal drivers H1–H4, and the SHP/SHD sample clocks.

A unique architecture makes it routine for the system designer to

optimize image quality by providing precise control over the hori-

zontal CCD readout and the AFE correlated double sampling.

Timing Resolution

The Precision Timing core uses a 1ϫ master clock input (CLI) as

a reference. This clock should be the same as the CCD pixel clock

frequency. Figure 4 illustrates how the internal timing core

divides the master clock period into 48 steps or edge positions.

Therefore, the edge resolution of the Precision Timing core is

(tCLI /48). For more information on using the CLI input, see the

Applications Information section.

POSITION

P[0]

CLI

tCLIDLY

1 PIXEL

PERIOD

P[12]

...

P[24]

P[36]

P[48]=P[0]

...

NOTES

1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.

2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (tCLIDLY = 6 ns TYP).

Figure 4. High Speed Clock Resolution from CLI Master Clock Input

REV. A

–15–

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