AD9629-65 データシートの表示（PDF） - Analog Devices

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AD9629-65

12-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter

Analog Devices 

AD9629

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Data Sheet

CLK+ 1

CLK– 2

AVDD 3

CSB 4

SCLK/DFS 5

SDIO/PDWN 6

NIC 7

NIC 8

AD9629

TOP VIEW

(Not to Scale)

24 AVDD

23 MODE/OR

22 DCO

21 D11 (MSB)

20 D10

19 D9

18 D8

17 D7

NOTES

1. NIC = NOT INTERNALLY CONNECTED.

2. THE EXPOSED PADDLE IS THE ONLY GROUND CONNECTION.

IT MUST BE SOLDERED TO THE ANALOG GROUND OF THE

CUSTOMER’S PCB TO ENSURE PROPER FUNCTIONALITY

AND MAXIMIZE HEAT DISSIPATION, NOISE, AND MECHANICAL

STRENGTH BENEFITS.

Figure 3. Pin Configuration

Table 8. Pin Function Description

Pin No.

Mnemonic Description

0 (EPAD)

GND

Exposed Paddle. The exposed paddle is the only ground connection. It must be soldered to the analog

ground of the customer’s PCB to ensure proper functionality and maximize heat dissipation, noise, and

mechanical strength benefits.

1, 2

CLK+, CLK− Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs.

3, 24, 29, 32

AVDD

1.8 V Supply Pin for ADC Core Domain.

4

CSB

SPI Chip Select. Active low enable. 30 kΩ internal pull-up.

5

SCLK/DFS SPI Clock Input in SPI Mode (SCLK). 30 kΩ internal pull-down.

Data Format Select in Non-SPI Mode (DFS). Static control of data output format. 30 kΩ internal pull-down.

DFS high = twos complement output; DFS low = offset binary output.

6

SDIO/PDWN SPI Data Input/Output (SDIO). Bidirectional SPI data I/O in SPI mode. 30 kΩ internal pull-down.

Non-SPI Mode Power-Down (PDWN). Static control of power-down with 30 kΩ internal pull-down. See

Table 14 for details.

7, 8

NIC

Not Internally Connected.

9 to 12, 14 to 21 D0 (LSB) to

D11 (MSB)

ADC Digital Outputs.

13

DRVDD

1.8 V to 3.3 V Supply Pin for Output Driver Domain.

22

DCO

Data Clock Digital Output.

23

MODE/OR Chip Mode Select Input or Out-of-Range (OR) Digital Output in SPI Mode.

Default = out-of-range (OR) digital output (SPI Register 0x2A[0] = 1).

Option = chip mode select input (SPI Register 0x2A[0] = 0).

Chip power down (SPI Register 0x08[7:5] = 100b).

Chip standby (SPI Register 0x08[7:5] = 101b).

Normal operation, output disabled (SPI Register 0x08[7:5] = 110b).

Normal operation, output enabled (SPI Register 0x08[7:5] = 111b).

Out-of-Range (OR) digital output only in non-SPI mode.

25

VREF

1.0 V Voltage Reference Input/Output. See Table 10.

26

SENSE

Reference Mode Selection. See Table 10.

27

VCM

Analog Output Voltage at Mid AVDD Supply. Sets common mode of the analog inputs.

28

RBIAS

Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground.

30, 31

VIN−, VIN+ ADC Analog Inputs.

Rev. B | Page 10 of 32

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