AD9629
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error1
Differential Nonlinearity (DNL)2
Integral Nonlinearity (INL)2
TEMPERATURE DRIFT
Offset Error
INTERNAL VOLTAGE REFERENCE
Output Voltage (1 V Mode)
Load Regulation Error at 1.0 mA
INPUT-REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 1.0 V
Input Capacitance3
Input Common-Mode Voltage
Input Common-Mode Range
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD2
IDRVDD2 (1.8 V)
IDRVDD2 (3.3 V)
POWER CONSUMPTION
DC Input
Sine Wave Input2 (DRVDD = 1.8 V)
Sine Wave Input2 (DRVDD = 3.3 V)
Standby Power4
Power-Down Power
Temp
Full
AD9629-20/AD9629-40
Min Typ
Max
12
Full
Guaranteed
Full −0.40 +0.05
+0.50
Full
−1.5
Full
±0.25
25°C
±0.11
Full
±0.40
25°C
±0.11
Full
±2
Full 0.984 0.996
Full
2
1.008
25°C
0.25
Full
2
Full
6
Full
0.9
Full 0.5
1.3
Full
7.5
Full 1.7 1.8
1.9
Full 1.7
3.6
Full
24.9/31.1 26.7/33.2
Full
1.5/2.5
Full
2.7/4.7
Full
45.0/56.7
Full
47.5/60.5 50.7/65.0
Full
53.7/71.7
Full
34
Full
0.5
AD9629-65
AD9629-80
Min Typ Max Min Typ Max Unit
12
12
Bits
Guaranteed
−0.40 +0.05 +0.50
−1.5
±0.25
±0.11
±0.30
±0.13
Guaranteed
−0.40 +0.05 +0.50
−1.5
±0.30
±0.16
±0.35
±0.16
% FSR
% FSR
LSB
LSB
LSB
LSB
±2
±2
ppm/°C
0.984 0.996 1.008 0.984 0.996 1.008 V
2
2
mV
0.25
0.25
LSB rms
2
2
V p-p
6
6
pF
0.9
0.9
V
0.5
1.3 0.5
1.3 V
7.5
7.5
kΩ
1.7 1.8 1.9 1.7 1.8 1.9 V
1.7
3.6 1.7
3.6 V
41.2 46.0
4.2
7.5
46.8 50.0 mA
5.0
mA
9.0
mA
75
81.7 86.0
98.9
34
0.5
85.2
mW
93 100 mW
114
mW
34
mW
0.5
mW
1 Measured with 1.0 V external reference.
2 Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit.
3 Input capacitance refers to the effective capacitance between one differential input pin and AGND.
4 Standby power is measured with a dc input and the clock active.
Rev. 0 | Page 4 of 32