AD9643BCPZ-170(RevE) データシートの表示（PDF） - Analog Devices
部品番号
コンポーネント説明
メーカー
AD9643BCPZ-170
(Rev.:RevE)
(Rev.:RevE)
Analog Devices
AD9643BCPZ-170 Datasheet PDF : 36 Pages
| |||
Data Sheet
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
tSSYNC
tHSYNC
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
tDIS_SDIO
Conditions
SYNC to the rising edge of CLK setup time
SYNC to the rising edge of CLK hold time
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Time required for the SDIO pin to switch from an input to an output
relative to the SCLK falling edge
Time required for the SDIO pin to switch from an output to an input
relative to the SCLK rising edge
AD9643
Min Typ Max Unit
1
0.3
ns
1
0.4
ns
2
ns
2
ns
40
ns
2
ns
2
ns
10
ns
10
ns
10
ns
10
ns
Rev. E | Page 9 of 36
Share Link: 