AD9628(Rev0) データシートの表示（PDF） - Analog Devices

部品番号

コンポーネント説明

メーカー

AD9628
(Rev.:Rev0)

12-Bit, 125/105 MSPS, 1.8 V Dual Analog-to-Digital Converter

Analog Devices 

AD9628

Pin No.

Mnemonic

Digital Outputs

11

B D1−/D0−(LSB)

12

B D1+/D0+(LSB)

13

B D3−/D2−

14

B D3+/D2+

15

B D5−/D4−

16

B D5+/D4+

17

B D7−/D6−

18

B D7+/D6+

20

B D9−/D8−

21

B D9+/D8+

22

B D11−/D10− (MSB)

23

B D11+/D10+ (MSB)

29

A D1−/D0−(LSB)

30

A D1+/D0+(LSB)

32

A D3−/D2−

31

A D3+/D2+

34

A D5+/D4+

33

A D5−/D4−

36

A D7+/D6+

35

A D7−/D6−

39

A D9+/D8_

38

A D9−/D8−

41

A D11+/D10+(MSB)

40

A D11−/D10−(MSB)

43

OR+

42

OR−

25

DCO+

24

DCO−

SPI Control

45

SCLK/DFS

44

SDIO/DCS

46

CSB

ADC Configuration

47

OEB

48

PDWN

Type

Description

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Channel B LVDS Output Data 1/Data 0—Complement.

Channel B LVDS Output Data 1/Data 0—True.

Channel B LVDS Output Data 3/Data 2—Complement.

Channel B LVDS Output Data 3/Data 2—True.

Channel B LVDS Output Data 5/Data 4—Complement.

Channel B LVDS Output Data 5/Data 4—True.

Channel B LVDS Output Data 7/Data 6—Complement.

Channel B LVDS Output Data 7/Data 6—True.

Channel B LVDS Output Data 9/Data 8—Complement.

Channel B LVDS Output Data 9/Data 8—True.

Channel B LVDS Output Data 11/Data 10—Complement.

Channel B LVDS Output Data 11/Data 10—True.

Channel A LVDS Output Data 1/Data 0—Complement.

Channel A LVDS Output Data 1/Data 0—True.

Channel A LVDS Output Data 3/Data 2—Complement.

Channel A LVDS Output Data 3/Data 2—True.

Channel A LVDS Output Data 5/Data 4—Complement.

Channel A LVDS Output Data 5/Data 4—True.

Channel A LVDS Output Data 7/Data 6—Complement.

Channel A LVDS Output Data 7/Data 6—True.

Channel A LVDS Output Data 9/Data 8—Complement.

Channel A LVDS Output Data 9/Data 8—True.

Channel A LVDS Output Data 11/Data 10—Complement.

Channel A LVDS Output Data 11/Data 10—True.

Channel A/Channel B LVDS Overrange Output—True.

Channel A/Channel B LVDS Overrange Output—Complement.

Channel A/Channel B LVDS Data Clock Output—True.

Channel A/Channel B LVDS Data Clock Output—Complement.

Input

Input/Output

Input

SPI Serial Clock/Data Format Select Pin in External Pin Mode.

SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.

SPI Chip Select (Active Low).

Input

Input

Output Enable Input (Active Low). Pin must be enabled via SPI.

Power-Down Input in External Pin Mode. In SPI mode, this input can be

configured as power-down or standby.

Rev. 0 | Page 18 of 44

Share Link: