AD9557BCPZ(RevA) データシートの表示（PDF） - Analog Devices

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AD9557BCPZ
(Rev.:RevA)

Dual Input Multiservice Line Card Adaptive Clock Translator

Analog Devices 

Data Sheet

–70

–80

–90

–100

–110

–120

–130

–140

–150

–160

10

INTEGRATED RMS JITTER (12kHz TO 20MHz): 391fs

100

1k

10k 100k 1M

10M 100M

FREQUENCY OFFSET (Hz)

Figure 13. Absolute Phase Noise (Output Driver = 3.3 V CMOS),

fR = 19.44 MHz, fO =161.1328125 MHz,

DPLL Loop BW = 0.1 Hz, fSYS = 19.2 MHz TCXO

–70

–80

–90

–100

–110

–120

–130

–140

–150

–160

10

INTEGRATED RMS JITTER (12kHz TO 20MHz): 395fs

100

1k

10k 100k 1M

10M 100M

FREQUENCY OFFSET (Hz)

Figure 14. Absolute Phase Noise (Output Driver = 1.8 V CMOS),

fR = 2 kHz, fO = 70.656 MHz,

DPLL Loop BW = 0.1 Hz, fSYS = 19.2 MHz TCXO

–60

INTEGRATED RMS JITTER (12kHz TO 20MHz): 388fs

–70

–80

–90

–100

–110

–120

–130

–140

–150

–160

10

100

1k

10k 100k 1M

10M 100M

FREQUENCY OFFSET (Hz)

Figure 15. Absolute Phase Noise (Output Driver = HSTL),

fR = 19.44 MHz, fO = 644.53 MHz, fSYS = 19.2 MHz TCXO, Holdover Mode

AD9557

2.0

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

FREQUENCY (MHz)

Figure 16. Amplitude vs. Toggle Rate,

HSTL Mode (LVPECL-Compatible Mode)

1.0

0.9

LVDS BOOST MODE

0.8

0.7

LVDS DEFAULT

0.6

0.5

0.4

0

100 200 300 400 500 600 700 800

FREQUENCY (MHz)

Figure 17. Amplitude vs. Toggle Rate, LVDS

3.5

3.3V CMOS

3.0

2.5

2.0

1.8V CMOS

1.5

1.0

0

50

100

150

200

250

300

FREQUENCY (MHz)

Figure 18. Amplitude vs. Toggle Rate with 10 pF Load,

3.3 V (Strong Mode) and 1.8 V CMOS

Rev. A | Page 21 of 92

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