AD9557(RevA) データシートの表示（PDF） - Analog Devices
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AD9557 Datasheet PDF : 92 Pages
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Data Sheet
AD9557
SERIAL PORT SPECIFICATIONS—I2C MODE
Table 16.
Parameter
SDA, SCL (AS INPUT)
Input Logic 1 Voltage
Input Logic 0 Voltage
Min
Typ
0.7 ×
DVDD3
Input Current
Hysteresis of Schmitt Trigger Inputs
Pulse Width of Spikes That Must Be Suppressed
by the Input Filter, tSP
SDA (AS OUTPUT)
Output Logic 0 Voltage
Output Fall Time from VIHmin to VILmax
TIMING
SCL Clock Rate
Bus-Free Time Between a Stop and Start Condition,
tBUF
Repeated Start Condition Setup Time, tSU; STA
Repeated Hold Time Start Condition, tHD;STA
−10
0.015 ×
DVDD3
20 + 0.1 Cb1
1.3
0.6
0.6
Max
0.3 ×
DVDD3
+10
50
0.4
250
400
Stop Condition Setup Time, tSU; STO
0.6
Low Period of the SCL Clock, tLOW
1.3
High Period of the SCL Clock, tHIGH
0.6
SCL/SDA Rise Time, tR
20 + 0.1 Cb1
300
SCL/SDA Fall Time, tF
20 + 0.1 Cb1
300
Data Setup Time, tSU; DAT
100
Data Hold Time, tHD; DAT
100
Capacitive Load for Each Bus Line, Cb1
400
1 Cb is the capacitance (pF) of a single bus line.
JITTER GENERATION
Jitter generation (random jitter) uses 49.152 MHz crystal for system clock input.
Table 17.
Parameter
JITTER GENERATION
Min
Typ
Max
fREF = 19.44 MHz; fOUT = 622.08 MHz; fLOOP = 50 Hz
HSTL Driver
Bandwidth: 5 kHz to 20 MHz
304
Bandwidth: 12 kHz to 20 MHz
296
Bandwidth: 20 kHz to 80 MHz
300
Bandwidth: 50 kHz to 80 MHz
266
Bandwidth: 16 MHz to 320 MHz
185
Unit Test Conditions/Comments
V
V
μA
For VIN = 10% to 90% DVDD3
ns
V
IO = 3 mA
ns
10 pF ≤ Cb ≤ 400 pF1
kHz
μs
μs
μs
After this period, the first clock pulse
is generated
μs
μs
μs
ns
ns
ns
ns
pF
Unit Test Conditions/Comments
System clock doubler enabled;
high phase margin mode enabled;
Register 0x0405 = 0x20; Register 0x0403 =
0x07; Register 0x0400 = 0x81; in cases
where multiple driver types are listed,
both driver types were tested at those
conditions, and the one with higher jitter
is quoted, although there is usually not
a significant jitter difference between
the driver types
fs rms
fs rms
fs rms
fs rms
fs rms
Rev. A | Page 13 of 92
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