AD9269-20EBZ(Rev0) データシートの表示（PDF） - Analog Devices
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AD9269-20EBZ
(Rev.:Rev0)
(Rev.:Rev0)
Analog Devices
AD9269-20EBZ Datasheet PDF : 40 Pages
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AD9269
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled,
unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate1
CLK Period—Divide-by-1 Mode (tCLK)
CLK Pulse Width High (tCH)
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
DATA OUTPUT PARAMETERS
Data Propagation Delay (tPD)
DCO Propagation Delay (tDCO)
DCO to Data Skew (tSKEW)
Pipeline Delay (Latency)
With QEC Active
Wake-Up Time2
Standby
OUT-OF-RANGE RECOVERY TIME
AD9269-20/AD9269-40
Temp Min Typ
Max
AD9269-65
AD9269-80
Min Typ Max Min Typ Max Unit
Full
480
480
480 MHz
Full 3
20/40 3
65 3
80 MSPS
Full 50/25
15.38
12.5
ns
25.0/12.5
7.69
6.25
ns
Full
1.0
1.0
1.0
ns
Full
0.1
0.1
0.1
ps rms
Full
3
Full
3
Full
0.1
Full
9
Full
11
Full
350
Full
600/400
Full
2
3
3
ns
3
3
ns
0.1
0.1
ns
9
9
Cycles
11
11
Cycles
350
350
μs
300
260
ns
2
2
Cycles
1 Conversion rate is the clock rate after the CLK divider.
2 Wake-up time is dependent on the value of the decoupling capacitors.
VIN
CLK+
CLK–
DCOA/DCOB
CH A/CH B DATA
N–1
tCH
tA
N
N+1
tCLK
N+2
N+3
N+4
N+5
tDCO
tSKEW
N–9
N–8
N–7
tPD
Figure 2. CMOS Output Data Timing
N–6
N–5
VIN
CLK+
CLK–
DCOA/DCOB
CH A/CH B DATA
N–1
tCH
tA
N
N+1
tCLK
N+2
N+3
N+4
N+5
tDCO
tSKEW
CH A CH B CH A CH B CH A
N–9 N–9 N–8 N–8 N–7
tPD
Figure 3. CMOS Interleaved Output Timing
Rev. 0 | Page 8 of 40
CH B
N–7
CH A
N–6
CH B
N–6
CH A
N–5
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