AD9228-65EB データシートの表示（PDF） - Analog Devices
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AD9228-65EB Datasheet PDF : 52 Pages
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AD9228
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 4.
Parameter1, 2
CLOCK 3
Maximum Clock Rate
Minimum Clock Rate
Clock Pulse Width High (tEH)
Clock Pulse Width Low (tEL)
OUTPUT PARAMETERS3
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
FCO Propagation Delay (tFCO)
DCO Propagation Delay (tCPD)4
DCO to Data Delay (tDATA)4
DCO to FCO Delay (tFRAME)4
Data to Data Skew
(tDATA-MAX − tDATA-MIN)
Wake-Up Time (Standby)
Wake-Up Time (Power-Down)
Pipeline Latency
APERTURE
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
Out-of-Range Recovery Time
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
25°C
25°C
25°C
AD9228-40
Min
Typ
Max
40
10
12.5
12.5
2.0
2.0
(tSAMPLE/24) − 300
(tSAMPLE/24) − 300
2.7
300
300
2.7
tFCO +
(tSAMPLE/24)
(tSAMPLE/24)
(tSAMPLE/24)
±50
3.5
3.5
(tSAMPLE/24) + 300
(tSAMPLE/24) + 300
±150
600
375
8
500
<1
1
AD9228-65
Min
Typ
Max
65
10
7.7
7.7
2.0
2.0
(tSAMPLE/24) − 300
(tSAMPLE/24) − 300
2.7
300
300
2.7
tFCO +
(tSAMPLE/24)
(tSAMPLE/24)
(tSAMPLE/24)
±50
3.5
3.5
(tSAMPLE/24) + 300
(tSAMPLE/24) + 300
±150
600
375
8
500
<1
2
Unit
MSPS
MSPS
ns
ns
ns
ps
ps
ns
ns
ps
ps
ps
ns
μs
CLK
cycles
ps
ps rms
CLK
cycles
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 Measured on standard FR-4 material.
3 Can be adjusted via the SPI.
4 tSAMPLE/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles.
Rev. B | Page 6 of 52
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