AD8328(Rev0) データシートの表示（PDF） - Analog Devices
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AD8328 Datasheet PDF : 16 Pages
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AD8328
LOGIC INPUTS (TTL/CMOS Compatible Logic) (DATEN, CLK, SDATA, TXEN, SLEEP, VCC = 5 V. Full Temperature Range.)
Parameter
Min
Typ
Max
Unit
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current (VINH = 5 V) CLK, SDATA, DATEN
Logic 0 Current (VINL = 0 V) CLK, SDATA, DATEN
Logic 1 Current (VINH = 5 V) TXEN
Logic 0 Current (VINL = 0 V) TXEN
Logic 1 Current (VINH = 5 V) SLEEP
Logic 0 Current (VINL = 0 V) SLEEP
2.1
0
0
–600
50
–250
50
–250
5.0
V
0.8
V
20
nA
–100
nA
190
µA
–30
µA
190
µA
–30
µA
Specifications subject to change without notice.
TIMING REQUIREMENTS (Full Temperature Range, VCC = 5 V, tR = tF = 4 ns, fCLK = 8 MHz, unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
Clock Pulsewidth (tWH)
16.0
Clock Period (tC)
32.0
Setup Time SDATA vs. Clock (tDS)
5.0
Setup Time DATEN vs. Clock (tES)
15.0
Hold Time SDATA vs. Clock (tDH)
5.0
Hold Time DATEN vs. Clock (tEH)
3.0
Input Rise and Fall Times, SDATA, DATEN, Clock (tR, tF)
Specifications subject to change without notice.
ns
ns
ns
ns
ns
ns
10
ns
tDS
SDATA
VALID DATA-WORD G1
MSB. . . .LSB
tC
tWH
VALID DATA-WORD G2
CLK
tES
tEH
DATEN
8 CLOCK CYCLES
GAIN TRANSFER (G1)
GAIN TRANSFER (G2)
TXEN
tOFF
tGS
tON
ANALOG
OUTPUT
SIGNAL AMPLITUDE (p-p)
Figure 2. Serial Interface Timing
VALID DATA BIT
SDATA MSB
MSB-1
MSB-2
CLK
tDS
tDH
REV. 0
Figure 3. SDATA Timing
–3–
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