AD7983
Data Sheet
VDD = 2.37 V to 2.63 V, VIO = 1.71 to 2.3 V, TA = −40°C to +85°C, unless otherwise stated. See Figure 2 for load conditions.
Table 5.
Parameter1
Throughput Rate
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions2
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
SCK Period (Chain Mode)
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (Chain Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
Symbol
tCONV
tACQ
tCYC
tCNVH
tSCK
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
tDIS
tSSDICNV
tHSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
Min
300
250
1.2
10
22
23
6
6
3
5
10
0
5
5
2
3
Typ Max Unit
833 kSPS
500 ns
ns
μs
ns
ns
ns
ns
ns
ns
14
21
ns
18
40
ns
20
ns
ns
ns
ns
ns
ns
ns
ns
22
ns
1 Timing parameters measured with respect to a falling edge are defined as triggered at x% VIO. Timing parameters measured with respect to a rising edge are defined
as triggered at y% VIO. For VIO ≤ 3 V, x = 90 and y = 10. For VIO > 3 V, x = 70 and y = 30. The minimum VIH and maximum VIL are used. See the Digital Inputs
Specifications in Table 2.
2 The time required to clock out N bits of data, tREAD, may be greater than tACQ depending on the magnitude of VIO. If tREAD is greater than tACQ, the throughput must be
limited to ensure that all N bits are read back from the device.
500µA IOL
TO SDO
CL
20pF
1.4V
500µA IOH
Figure 2. Load Circuit for Digital Interface Timing
Rev. C | Page 6 of 25