AD7961BCPZ データシートの表示（PDF） - Analog Devices
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AD7961BCPZ Datasheet PDF : 24 Pages
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Data Sheet
AD7961
Parameter
Test Conditions/Comments
Min
Power-Down
EN3 to EN0 = X000
VDD1
VDD2
VIO
Power Dissipation
Static—Not Converting, Internal
Reference Buffer Disabled
Self clocked mode, CNV± in CMOS
mode9
Static—Not Converting, Internal
Reference Buffer Enabled
Self clocked mode, CNV± in CMOS
mode9
Converting: Internal Reference Buffer Echoed clock mode, CNV± in LVDS
Disabled
mode
Converting: Internal Reference Buffer Echoed clock mode, CNV± in LVDS
Enabled
mode
Converting: Internal Reference Buffer Self clocked mode, CNV± in CMOS
Disabled
mode9
Power-Down
EN3 to EN0 = X000
Energy per Conversion
Self clocked, CNV± in CMOS mode9
TEMPERATURE RANGE
Specified Performance
TMIN to TMAX
−40
Typ Max
1
2.8
1
37.8
0.2
4.6
9
10.3
21
25
46.5
56.2
64.5
76.4
39
47.4
7.2
94.5
7.8
9.5
+85
Unit
μA
μA
μA
mW
mW
mW
mW
mW
μW
nJ/sample
°C
1 The minimum and maximum values are guaranteed by characterization.
2 Using an external reference.
3 See Table 9 for logic levels of enable pins. When EN2 = 1, the −3 dB input bandwidth is 9 MHz. Use this lower bandwidth only when the throughput rate is 2 MSPS or
lower.
4 The oversampled dynamic range is the ratio of the peak signal power to the noise power (for a small input) measured in the ADC output FFT from dc up to fS/(2 × OSR),
where fS is the ADC sample rate and OSR is the oversampling ratio.
5 Guaranteed by design.
6 The REFIN pin is tied to 0 V in this mode.
7 The ANSI-644 LVDS specification has a minimum common-mode output (VOCM) of 1125 mV.
8 The current dissipated in the VCM circuitry when enabled is REF/20 kΩ and is not included in the operating currents listed.
9 CNV+ works as a CMOS input when CNV− is grounded. See Table 7 for additional information.
TIMING SPECIFICATIONS
VDD1 = 5 V; VDD2 = 1.8 V; VIO = 1.71 V to 1.89 V; REF = 5 V or 4.096 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Time Between Conversions
Acquisition Time
CNV± High Time
CNV± to D± (MSB) Ready
CNV± to Last CLK± (LSB) Delay
CLK± Period1
CLK± Frequency
CLK± to DCO± Delay (Echoed Clock Mode)
DCO± to D± Delay (Echoed Clock Mode)
CLK± to D± Delay
Symbol
tCYC
tACQ
tCNVH
tMSB
tCLKL
tCLK
fCLK
tDCO
tD
tCLKD
Min Typ
Max
200
tCYC − 115
10
0.6 × tCYC
200
160
3.33 4
(tCYC − tMSB + tCLKL)/n
250
300
0
3
5
0
1
0
3
5
Unit
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
1 For the maximum CLK± period, the window available to read data is tCYC − tMSB + tCLKL. Divide this time by the number of bits (n) to be read giving the maximum CLK±
frequency that can be used for a given conversion CNV± frequency. In echoed clock interface mode, n = 16; in self clocked interface mode, n = 18.
Rev. B | Page 5 of 24
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