AD7622 データシートの表示（PDF） - Analog Devices
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AD7622 Datasheet PDF : 28 Pages
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AD7622
Pin
No. Mnemonic
24
D11
or RDERROR
25 to
28
29
D[12:15]
BUSY
30
DGND
31
RD
Type1
DO
DO
DO
P
DI
Description
When SER/PAR = low, this output is used as Bit 11 of the parallel port data output bus.
When SER/PAR = high, read error. In serial slave mode (EXT/INT = high), this output
is used as an incomplete read error flag. If a data read is started and not completed when the
current conversion is complete, the current data is lost and RDERROR is pulsed high.
Bit 12 to Bit 15 of the parallel port data output bus. These pins are always outputs, regardless of
the interface mode.
Busy Output. Transitions high when a conversion is started and remains high until the conversion
is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be
used as a data-ready clock signal.
Digital Power Ground.
Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled.
32
CS
33
RESET
34
PD
35
CNVST
37
REF
38
REFGND
39
IN−
40
NC
43
IN+
45
TEMP
46
REFBUFIN
47
PDREF
48
PDBUF
DI
Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled.
CS is also used to gate the external clock in slave serial mode.
DI
Reset Input. When high, resets the AD7622. Current conversion, if any, is aborted. Falling edge of
RESET enables the calibration mode indicated by pulsing BUSY high. Refer to the RESET section.
If not used, this pin can be tied to DGND.
DI
Power-Down Input. When high, power downs the ADC. Power consumption is reduced and
conversions are inhibited after the current one is completed.
DI
Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state
and initiates a conversion.
AI/O Reference Output/Input.
When PDREF/PDBUF = low, the internal reference and buffer are enabled producing 2.048 V on this pin.
When PDREF/PDBUF = high, the internal reference and buffer are disabled allowing an externally
supplied voltage reference up to AVDD volts. Decoupling is required with or without the internal
reference and buffer. Refer to the Voltage Reference Input section.
AI
Reference Input Analog Ground.
AI
Differential Negative Analog Input.
No Connect.
AI
Differential Positive Analog Input.
AO Temperature Sensor Analog Output. Normally, 278 mV @ 25°C with a temperature coefficient of
1 mV/°C. This pin can be used to measure the temperature of the AD7622. See the
Temperature Sensor section.
AI/O Internal Reference Output/Reference Buffer Input.
When PDREF/PDBUF = low, the internal reference and buffer are enabled producing the 1.2 V (typical)
band gap output on this pin, which needs external decoupling. The internal fixed gain reference
buffer uses this to produce 2.048 V on the REF pin.
When using an external reference with the internal reference buffer (PDBUF = low, PDREF = high),
applying 1.2 V on this pin produces 2.048 V on the REF pin. Refer to the Voltage Reference Input section.
DI
Internal Reference Power-Down Input.
When low, the internal reference is enabled.
When high, the internal reference is powered down and an external reference must been used.
DI
Internal Reference Buffer Power-Down Input.
When low, the buffer is enabled (must be low when using internal reference).
When high, the buffer is powered-down.
1 AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power.
2 With an SCLK period ≥ (2 × t32). With an SCLK period < (2 × t32), SDOUT is valid on the next rising edge with INVSCLK = low and next falling edge with INVSCLK = high.
Rev. A | Page 10 of 28
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