AD7329BRUZ データシートの表示（PDF） - Analog Devices

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AD7329BRUZ

1 MSPS, 8-Channel, Software-Selectable, True Bipolar Input, 12-Bit Plus Sign ADC

Analog Devices 

AD7329

MODES OF OPERATION

The AD7329 has several modes of operation that are designed

to provide flexible power management options. These options

can be chosen to optimize the power dissipation/throughput

rate ratio for different application requirements. The mode of

operation of the AD7329 is controlled by the power management

bits, Bit PM1 and Bit PM0, in the control register as shown in

Table 13. The default mode is normal mode, where all internal

circuitry is fully powered up.

NORMAL MODE

(PM1 = PM0 = 0)

This mode is intended for the fastest throughput rate

performance with the AD7329 being fully powered up at all

times. Figure 52 shows the general operation of the AD7329

in normal mode.

The conversion is initiated on the falling edge of CS, and the

track-and-hold section enters hold mode, as described in the

Serial Interface section. The data on the DIN line during the

16 SCLK transfer is loaded into one of the on-chip registers if

the write bit is set. The register is selected by programming the

register select bits (see Table 10).

CS

1

16

SCLK

DOUT

DIN

3 CHANNEL I.D. BITS, SIGN BIT + CONVERSION RESULT

DATA INTO CONTROL/SEQUENCE/RANGE1/RANGE2

REGISTER

Figure 52. Normal Mode

The AD7329 remains fully powered up at the end of the

conversion if both PM1 and PM0 contain 0 in the control

register.

To complete the conversion and access the conversion result,

16 serial clock cycles are required. At the end of the conversion,

CS can idle either high or low until the next conversion.

After the data transfer is complete, another conversion can be

initiated after the quiet time, tQUIET, has elapsed.

FULL SHUTDOWN MODE

(PM1 = PM0 = 1)

In this mode, all internal circuitry on the AD7329 is powered

down. The part retains information in the registers during full

shutdown. The AD7329 remains in full shutdown mode until

the power management bits, Bit PM1 and Bit PM0, in the

control register are changed.

A write to the control register with PM1 = PM0 = 1 places the

part into full shutdown mode. The AD7329 enters full shutdown

mode on the 15th SCLK rising edge when the control register is

updated.

If a write to the control register occurs while the part is in full

shutdown mode with the power management bits, Bit PM1 and

Bit PM0, set to 0 (normal mode), the part begins to power up on

the 15th SCLK rising edge when the control register is updated.

Figure 53 shows how the AD7329 is configured to exit full

shutdown mode. To ensure that the AD7329 is fully powered

up, tPOWER-UP should elapse before the next CS falling edge.

PART IS IN FULL

SHUTDOWN

CS

THE PART BEGINS TO POWER UP ON THE

15TH SCLK RISING EDGE AS PM1 = PM0 = 0

THE PART IS FULLY POWERED UP

ONCE tPOWER-UP HAS ELAPSED

tPOWER-UP

1

16

1

16

SCLK

SDATA

INVALID DATA

CHANNEL IDENTIFIER BITS + CONVERSION RESULT

DIN

DATA INTO CONTROL REGISTER

DATA INTO CONTROL/SHADOW REGISTER

CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS.

PM1 = PM0 = 0

TO KEEP THE PART IN NORMAL MODE, LOAD PM1 = PM0 = 0

IN CONTROL REGISTER

Figure 53. Exiting Full Shutdown Mode

Rev. A | Page 32 of 40

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