AD7327BRUZ データシートの表示（PDF） - Analog Devices
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AD7327BRUZ
Analog Devices
AD7327BRUZ Datasheet PDF : 36 Pages
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AD7327
TIMING SPECIFICATIONS
VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V to 3.0 V internal/external,
TA = TMAX to TMIN. Timing specifications apply with a 32 pF load, unless otherwise noted.1
Table 3.
Parameter
fSCLK
tCONVERT
tQUIET
t1
t2 2
t3
t4
t5
t6
t7
t8
t9
t10
tPOWER-UP
Limit at TMIN, TMAX
VCC < 4.75 V
50
VCC = 4.75 V to 5.25 V
50
10
10
16 × tSCLK
75
16 × tSCLK
60
12
5
25
20
45
35
26
14
57
43
0.4 × tSCLK
0.4 × tSCLK
13
0.4 × tSCLK
0.4 × tSCLK
8
40
22
10
9
4
4
2
2
750
750
500
500
Unit
kHz min
MHz max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns max
μs max
25
25
μs typ
Description
VDRIVE ≤ VCC
tSCLK = 1/fSCLK
Minimum time between end of serial read and next falling edge of CS
Minimum CS pulse width
CS to SCLK set-up time; bipolar input ranges (±10 V, ±5 V, ±2.5 V)
Unipolar input range (0 V to 10 V)
Delay from CS until DOUT three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
SCLK falling edge to DOUT high impedance
SCLK falling edge to DOUT high impedance
DIN set-up time prior to SCLK falling edge
DIN hold time after SCLK falling edge
Power-up from autostandby
Power-up from full shutdown/autoshutdown mode, internal
reference
Power-up from full shutdown/autoshutdown mode, external
reference
1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
2 When using the 0 V to 10 V unipolar range, running at 500 kSPS throughput rate with t2 at 20 ns, the mark space ratio needs to be limited to 50:50.
CS
t2
SCLK
1
2
3
3 IDENTIFICATION BITS
t3
DOUT
ADD1 ADD0 SIGN
THREE- ADD2
STATE
t9
tCONVERT
t6
4
5
t4 t7
DB11 DB10
t10
DIN
WRITE
REG
SEL1
REG
SEL2
MSB
t1
13
14
t5
DB2 DB1
15
DB0
16
t8
tQUIET
THREE-STATE
LSB
DON’T
CARE
Figure 2. Serial Interface Timing Diagram
Rev. 0 | Page 7 of 36
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