AD7291BCPZ データシートの表示（PDF） - Analog Devices
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AD7291BCPZ Datasheet PDF : 28 Pages
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Data Sheet
The example in Figure 28 shows the command mode convert-
ing on a sequence of channels including VIN0, VIN1, and VIN2.
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device (AD7291) asserts an
acknowledge on SDA.
4. The master sends the command register address (0x00).
5. The slave asserts an acknowledge on SDA.
6. The master sends the first data byte (0xE0) to the command
register, which selects the VIN0, VIN1, and VIN2 channels.
7. The slave asserts an acknowledge on SDA.
8. The master sends the second data byte (0x20) to the com-
mand register.
9. The slave asserts an acknowledge on SDA.
10. The master sends the result register address (0x01).
11. The slave asserts an acknowledge on SDA. An optional
repeated start (SR) command can be asserted at this point
to ensure the bus is not relinquished by the master.
12. The master sends the 7-bit slave address followed by the
read bit (high).
13. The slave (AD7291) asserts an acknowledge on SDA.
AD7291
14. The master receives a data byte, which contains the four
channel address bits and the four MSBs of the converted
result for Channel VIN0.
15. The master then asserts an acknowledge on SDA.
16. The master receives the second data byte, which contains
the eight LSBs of the converted result for Channel VIN0. The
master then asserts an acknowledge on SDA.
17. Step 14 to Step 16 are repeated for Channel VIN1 and
Channel VIN2.
18. Once the master has received the results from all the
selected channels, the slave again converts and outputs
the result for the first channel in the selected sequence.
Step 14 to Step 16 are repeated.
19. The master asserts a not acknowledge on SDA and a stop
condition on SDA to end the conversion and exit
command mode.
To change the conversion sequence, rewrite a new sequence to
the command mode. If a new write to the command register is
performed while an existing conversion sequence is underway,
the existing conversion sequence is terminated and the next
conversion performed is the first selected channel from the new
sequence. The maximum throughput that can be achieved using
this mode with a 400 kHz I2C clock is (400 kHz/18) = 22.2 kSPS.
S SLAVE ADDRESS 0 SA
POINT TO COMMAND REG (0x00)
SA
COMMAND = 0xE0
SA
COMMAND = 0x20
SA
...
POINT TO RESULT REG (0x01)
SA SR SLAVE ADDRESS
*
1 SA CH AD (0000)
VIN0[11:8]
A ...
...
*
VIN0[7:0]
A CH AD (0001)
VIN1[11:8]
A
VIN1[7:0]
A ...
... *
CH AD (0010)
VIN2[11:8]
A
VIN2[7:0]
*
A CH ID (0000)
VIN0[11:8]
A ...
... VIN0[7:0] A ........
* = POSITION OF SAMPLING START
VIN2[7:0]
AP
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
Figure 28. Command Mode Operation
S = START CONDITION
SR = REPEATED START
P = STOP CONDITION
SA = SLAVE ACKNOWLEDGE
A = NOT ACKNOWLEDGE
Rev. C | Page 25 of 28
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