EVAL-AD7091RSDZ データシートの表示（PDF） - Analog Devices
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EVAL-AD7091RSDZ Datasheet PDF : 20 Pages
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Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD7091R
VDD 1
REFIN/REFOUT 2
VIN 3
REGCAP 4
GND 5
AD7091R
TOP VIEW
(Not to Scale)
10 VDRIVE
9 SDO
8 SCLK
7 CS
6 CONVST
NOTES
1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY.
FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND
FOR MAXIMUM THERMAL CAPABILITY, SOLDER THE EXPOSED
PAD TO THE SUBSTRATE, GND.
Figure 3. Pin Configuration, 10-Lead LFCSP
VDD 1
REFIN/REFOUT 2
VIN 3
REGCAP 4
GND 5
10 VDRIVE
AD7091R
TOP VIEW
(Not to Scale)
9 SDO
8 SCLK
7 CS
6 CONVST
Figure 4. Pin Configuration, 10-Lead MSOP
Table 5. Pin Function Descriptions
Pin No.
LFCSP MSOP
Mnemonic Description
1
1
VDD
Power Supply Input. The VDD range is from 2.7 V to 5.25 V. This supply pin should be decoupled to
GND. The typical recommended values are 10 μF and 0.1 μF.
2
2
REFIN/REFOUT
Voltage Reference Input Output. Decouple this pin to GND. The typical recommended decoupling
capacitor value is 2.2 μF. The user can either access the internal 2.5 V reference or overdrive the
internal reference with an externally applied voltage. The reference voltage range for an externally
applied reference is 2.7 V to VDD.
3
3
VIN
Analog Input. The single-ended analog input range is from 0 V to VREF.
4
4
REGCAP
Decoupling Capacitor Pin for Voltage Output from Internal Regulator. This output pin should be
decoupled separately to GND using a 1 μF capacitor. The voltage at this pin is 1.8 V typical.
5
5
GND
Analog Ground. This pin is the ground reference point for all circuitry on the AD7091R. The analog
input signal should be referred to this GND voltage.
6
6
CONVST
Convert Start. Active low edge triggered logic input. The falling edge of CONVST places the track-
and-hold into hold mode and initiates a conversion.
7
7
CS
Chip Select. Active low logic input. The serial bus is enabled when CS is held low, and in this mode CS
is used to frame the output data on the SPI bus.
8
8
SCLK
Serial Clock. This pin acts as the serial clock input.
9
9
SDO
Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits
are clocked out on the falling edge of the SCLK input. The data is provided MSB first.
10
10
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines the operating voltage of the
interface. Decoupling capacitors should be connected between VDRIVE and GND. The typical
recommended values are 10 μF and 0.1 μF. The voltage range of this pin is 1.65 V to 5.25 V.
11
N/A
EPAD
Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder
joints and for maximum thermal capability, solder the exposed pad to the substrate, GND.
Rev. B | Page 7 of 20
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