AD7819YRU(RevA) データシートの表示（PDF） - Analog Devices

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AD7819YRU
(Rev.:RevA)

+2.7 V to +5.5 V, 200 kSPS 8-Bit Sampling ADC

Analog Devices 

EXT CONVST

INT CONVST

BUSY

tPOWER-UP

t1

t2

t3

CS/RD

DB7–DB0

EXT CONVST

INT CONVST

BUSY

CS/RD

DB7–DB0

8 MSBs

Figure 13. Mode 1 Operation

tPOWER-UP

t1

t3

8 MSBs

Figure 14. Mode 2 Operation

AD7819

PARALLEL INTERFACE

The parallel interface of the AD7819 is eight bits wide. The out-

put data buffers are activated when both CS and RD are logic

low. At this point the contents of the data register are placed on

the 8-bit data bus. Figure 15 shows the timing diagram for the par-

allel port. The Parallel Interface of the AD7819 is reset when

BUSY goes logic high. Care must be taken to ensure that a read

operation does not occur while BUSY is high. Data read from

the AD7819 while BUSY is high will be invalid. For optimum

performance the read operation should end at least 100 ns (t8)

prior to the falling edge of the next CONVST.

CONVST

t2

t3

BUSY

t1

CS

RD

DB7–DB0

t8

t4

t5

t7

t6

8 MSBs

Figure 15. Parallel Port Timing

REV. A

–9–

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