AD7819(RevA) データシートの表示（PDF） - Analog Devices
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AD7819 Datasheet PDF : 11 Pages
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AD7819
MICROPROCESSOR INTERFACING
The parallel port on the AD7819 allows the device to be inter-
faced to a range of many different microcontrollers. This section
explains how to interface the AD7819 with some of the more
common microcontroller parallel interface protocols.
AD7819 to 8051
Figure 16 shows a parallel interface between the AD7819 and
the 8051 microcontroller. The BUSY signal on the AD7819 pro-
vides an interrupt request to the 8051 when a conversion begins.
Port 0 of the 8051 may serve as an input or output port, or as in
this case when used together, may be used as a bidirectional
low-order address and data bus. The address latch enable out-
put of the 8051 is used to latch the low byte of the address
during accesses to the device, while the high-order address byte
is supplied from Port 2. Port 2 latches remain stable when the
AD7819 is addressed, as they do not have to be turned around
(set to 1) for data input as is the case for Port 0.
8051*
AD0–AD7
DB0–DB7
LATCH DECODER
AD7819*
ALE
CS
A8–A15
RD
RD
INT
BUSY
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 16. Interfacing to the 8051
AD7819 to PIC16C6x/7x
Figure 17 shows a parallel interface between the AD7819 and the
PIC16C64/65/74. The BUSY signal on the AD7819 provides
an interrupt request to the microcontroller when a conversion
begins. Of the PIC16C6x/7x range of microcontrollers, only
the PIC16C64/65/74 can provide the option of a parallel slave
port. Port D of the microcontroller will operate as an 8-bit
wide parallel slave port when control bit PSPMODE in the
TRISE register is set. Setting PSPMODE enables the port pin
RE0 to be the RD output and RE2 to be the CS output. For
this functionality, the corresponding data direction bits of the
TRISE register must be configured as outputs (reset to 0). See
user PIC16/17 Microcontroller User Manual.
PSP0–PSP7
PIC16C6x/7x*
CS
DB0–DB7
AD7819*
CS
RD
RD
INT
BUSY
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 17. Interfacing to the PIC16C6x/7x
AD7819 to ADSP-21xx
Figure 18 shows a parallel interface between the AD7819 and
the ADSP-21xx series of DSPs. As before, the BUSY signal on
the AD7819 provides an interrupt request to the DSP when a
conversion begins.
D0–D7
DB0–DB7
A13–A0
ADSP-21xx*
DMS
ADDRESS
DECODE
LOGIC
EN
AD7819*
CS
RD
RD
IRQ
BUSY
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 18. Interfacing to the ADSP-21xx
–10–
REV. A
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