AD5170BRM2.5-RL7(RevA) データシートの表示（PDF） - Analog Devices

部品番号

コンポーネント説明

メーカー

AD5170BRM2.5-RL7
(Rev.:RevA)

256-Position Two-Time Programmable I2C Digital Potentiometer

Analog Devices 

AD5170

ESD PROTECTION

All digital inputs—SDA, SCL, AD0, and AD1—are protected

with a series input resistor and parallel Zener ESD structures, as

shown in Figure 34 and Figure 35.

340Ω

LOGIC

GND

Figure 34. ESD Protection of Digital Pins

A, B, W

GND

Figure 35. ESD Protection of Resistor Terminals

TERMINAL VOLTAGE OPERATING RANGE

The AD5170 VDD to GND power supply defines the boundary

conditions for proper 3-terminal digital potentiometer opera-

tion. Supply signals present on Terminal A, Terminal B, and

Terminal W that exceed VDD or GND will be clamped by the

internal forward-biased diodes (see Figure 36).

VDD

A

W

B

fuse programming supply (either an on-board regulator or

rack-mount power supply) must be rated at 5.25 V to 5.5 V and

able to provide a 100 mA current for 400 ms for successful one-

time programming. Once fuse programming is completed, the

VDD_OTP supply must be removed to allow normal operation at

2.7 V to 5.5 V and the device will consume current in µA range.

Figure 37 shows the simplest implementation of a dual supply

requirement by using a jumper. This approach saves one voltage

supply, but draws additional current and requires manual

configuration.

5.5V

R1 50kΩ

R2 250kΩ

CONNECT J1 HERE

FOR OTP

C1

C2

10µF 1nF

VDD

AD5170

CONNECT J1 HERE

AFTER OTP

Figure 37. Power Supply Requirement

An alternate approach in 3.5 V to 5.25 V systems adds a signal

diode between the system supply and the OTP supply for

isolation, as shown in Figure 38.

5.5V

3.5V–5.25V

APPLY FOR OTP ONLY

D1

C1

C2

1µF 1nF

VDD

AD5170

GND

Figure 36. Maximum Terminal Voltages Set by VDD and GND

POWER-UP SEQUENCE

Because the ESD protection diodes limit the voltage compliance

at Terminal A, Terminal B, and Terminal W (see Figure 36), it is

important to power VDD/GND before applying any voltage to

Terminal A, Terminal B, and Terminal W. Otherwise, the diode

will be forward biased such that VDD is powered unintentionally

and may affect the rest of the user’s circuit. The ideal power-up

sequence is GND, VDD, the digital inputs, and then VA/VB/VW.

The relative order of powering VA, VB, VW, and the digital

inputs is not important as long as they are powered after

VDD/GND.

POWER SUPPLY CONSIDERATIONS

To minimize the package pin count, both the one-time pro-

gramming and normal operating voltage supplies share the

same VDD terminal of the AD5170. The AD5170 employs fuse

link technology that requires 5.25 V to 5.5 V for blowing the

internal fuses to achieve a given setting, but normal VDD can be

anywhere between 2.7 V and 5.5 V after the fuse programming

process. As a result, dual voltage supplies and isolation are

needed if system VDD is lower than the required VDD_OTP. The

Figure 38. Isolate 5.5 V OTP Supply from 3.5 V to 5.25 V Normal Operating

Supply. The VDD_OTP must be removed once OTP is completed.

5.5V

R1

10kΩ

2.7V

P1

APPLY FOR OTP ONLY

C1

C2

P2 10µF 1nF

VDD

AD5170

P1=P2=FDV302P, NDS0610

Figure 39. Isolate 5.5 V OTP Supply from 2.7 V Normal Operating Supply.

The VDD_OTP supply must be removed once OTP is completed.

For users who operate their systems at 2.7 V, use of the

bidirectional low threshold P-Ch MOSFETs is recommended

for the supply’s isolation. As shown in Figure 39, this assumes

Rev. A | Page 14 of 24

Share Link: