AD5124BRUZ100 データシートの表示（PDF） - Analog Devices

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AD5124BRUZ100

Quad Channel, 128-/256-Position, I2C/SPI, Nonvolatile Digital Potentiometer

Analog Devices 

AD5124/AD5144/AD5144A

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagrams—TSSOP ............................................ 3

Specifications..................................................................................... 4

Electrical Characteristics—AD5124 .......................................... 4

Electrical Characteristics—AD5144 and AD5144A................ 7

Interface Timing Specifications ................................................ 10

Shift Register and Timing Diagrams ....................................... 11

Absolute Maximum Ratings.......................................................... 13

Thermal Resistance .................................................................... 13

ESD Caution................................................................................ 13

Pin Configurations and Function Descriptions ......................... 14

Typical Performance Characteristics ........................................... 17

Test Circuits..................................................................................... 22

Theory of Operation ...................................................................... 23

REVISION HISTORY

7/2019—Rev. B to Rev. C

Added Endnote 2, Table 14 ........................................................... 26

Added Endnote 2, Table 20 ........................................................... 29

Updated Outline Dimensions ....................................................... 33

7/2017—Rev. A to Rev. B

Changed LFCSP_WQ to LFCSP.................................. Throughout

Changes to Features Section............................................................ 1

Changes to Logic Supply Current Parameter, Table 2 ................. 5

Added Note 12 to Data Retention Parameter, Table 2;

Renumbered Sequentially................................................................ 6

Changes to Logic Supply Current Parameter, Table 3 ................. 8

Added Note 12 to Data Retention Parameter, Table 3;

Renumbered Sequentially................................................................ 9

Data Sheet

RDAC Register and EEPROM.................................................. 23

Input Shift Register .................................................................... 23

Serial Data Digital Interface Selection, DIS............................ 23

SPI Serial Data Interface............................................................ 23

I2C Serial Data Interface ............................................................ 25

I2C Address.................................................................................. 25

Advanced Control Modes ......................................................... 27

EEPROM or RDAC Register Protection ................................. 28

Load RDAC Input Register (LRDAC) ..................................... 28

RDAC Architecture.................................................................... 31

Programming the Variable Resistor......................................... 31

Programming the Potentiometer Divider ............................... 32

Terminal Voltage Operating Range ......................................... 32

Power-Up Sequence ................................................................... 32

Layout and Power Supply Biasing ............................................ 32

Outline Dimensions ....................................................................... 33

Ordering Guide .......................................................................... 34

Changes to Table 7.......................................................................... 13

Changes to Figure 11 and Table 11 .............................................. 16

Changes to Figure 20...................................................................... 18

Added Figure 21; Renumbered Sequentially .............................. 18

Changes to Figure 24...................................................................... 19

Change to Linear Gain Setting Mode Section ............................ 27

Change to RDAC Architecture Section ....................................... 31

Updated Outline Dimensions ....................................................... 33

12/2012—Rev. 0 to Rev. A

Changes to Table 12 and Table 13 ................................................ 25

10/2012—Revision 0: Initial Version

Rev. C | Page 2 of 36

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