AD1865R データシートの表示（PDF） - Analog Devices
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AD1865R Datasheet PDF : 12 Pages
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AD1865
ABSOLUTE MAXIMUM RATINGS*
VL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 6.0 V
VS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 6.0 V
–VS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –6.0 V to 0 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 0.3 V
Digital Inputs to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 to VL
Short Circuit Protection . . . . . . . . Indefinite Short to Ground
Soldering (10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1865 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model
AD1865N
AD1865N-J
AD1865R
AD1865R-J
Temperature
Range
–25°C to +70°C
–25°C to +70°C
–25°C to +70°C
–25°C to +70°C
Package
THD+N @ FS Option*
0.006%
0.004%
0.006%
0.004%
N-24A
N-24A
R-28
R-28
*N = Plastic DIP, R = Small Outline IC Package.
PIN DESIGNATIONS
DIP SOIC
11 22
12 23
–VS Negative Analog Supply
TRIM Right Channel Trim Network Connection
13 24
MSB Right Channel Trim Potentiometer
Wiper Connection
14 26
15 28
IOUT Right Channel Output Current
AGND Analog Common Pin
16 11
SJ
Right Channel Amplifier Summing Junction
17 12
18 13
19 14
10 15
RF
VOUT
+VL
DR
Right Channel Feedback Resistor
Right Channel Output Voltage
Positive Digital Supply
Right Channel Data Input Pin
11 16
LR Right Channel Latch Pin
12 17
CLK Clock Input Pin
13 18
DGND Digital Common Pin
14 19
LL Left Channel Latch Pin
15 10
DL Left Channel Data Input Pin
16 11, 16, 18 NC No Internal Connection*
25, 27
17 12
18 13
19 14
VOUT
RF
SJ
Left Channel Output Voltage
Left Channel Feedback Resistor
Left Channel Amplifier Summing Junction
20 15
AGND Analog Common Pin
21 17
22 19
IOUT Left Channel Output Current
MSB Left Channel Trim Potentiometer
Wiper Connection
23 20
TRIM Left Channel Trim Network Connection
24 21
+VS Positive Analog Supply
*Pin 16 has no internal connection; –VL from AD1864 DIP socket can be safely
applied.
PINOUT
(24-Pin DIP Package)
–VS 1
TRIM 2
24 +VS
23 TRIM
MSB 3
RIGHT
CHANNEL IOUT 4
AGND 5
SJ 6
RF 7
VOUT 8
+VL 9
AD1865
TOP VIEW
(Not to Scale)
DR 10
LR 11
CLK 12
22 MSB
21 IOUT
LEFT
CHANNEL
20 AGND
19 SJ
18 RF
17 VOUT
16 NC
15 DL
14 LL
13 DGND
NC = NO CONNECT
(28-Pin SOIC Package)
SJ 1
RF 2
VOUT 3
+VL 4
DR 5
LR 6
CLK 7
DGND 8
LL 9
DL 10
NC 11
VOUT 12
RF 13
SJ 14
AD1865
TOP VIEW
(Not to Scale)
28 AGND
27 NC
26 IOUT
25 NC
24 MSB
23 TRIM
22 –VS
21 +VS
20 TRIM
19 MSB
18 NC
17 IOUT
16 NC
15 AGND
NC = NO CONNECT
REV. 0
–3–
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