7546 Group
On-going Routine
Store Return Address
on Stack
Interrupt request
(Note)
Execute JSR
M (S) (PCH)
(S) (S – 1)
M (S) (PCL)
(S) (S – 1)
Subroutine
Restore Return
Address
Execute RTS
(S) (S + 1)
(PCL) M (S)
(S) (S + 1)
(PCH) M (S)
M (S) (PCH)
(S) (S – 1)
M (S) (PCL)
Store Return Address
on Stack
(S) (S – 1)
M (S) (PS)
Store Contents of Processor
Status Register on Stack
(S) (S – 1)
Interrupt
Service Routine
Execute RTI
(S) (S + 1)
(PS) M (S)
I Flag “0” to “1”
Fetch the Jump Vector
Restore Contents of
Processor Status Register
(S) (S + 1)
(PCL) M (S)
(S) (S + 1)
Restore Return
Address
(PCH) M (S)
Note : The condition to enable the interrupt Interrupt enable bit is “1”
Interrupt disable flag is “0”
Fig. 9 Register push and pop at interrupt generation and subroutine call
Table 4 Push and pop instructions of accumulator or processor status register
Accumulator
Processor status register
Push instruction to stack
PHA
PHP
Pop instruction from stack
PLA
PLP
Rev.1.21 Nov 15, 2006 page 11 of 93
REJ03B0160-0121