74LVT16374G(2002) データシートの表示（PDF） - Fairchild Semiconductor

部品番号

コンポーネント説明

メーカー

74LVT16374G
(Rev.:2002)

Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs

Fairchild Semiconductor 

Connection Diagrams

Pin Descriptions

Pin Assignment for SSOP and TSSOP

Pin Names

Description

OEn

CPn

I0–I15

O0–O15

NC

Output Enable Input (Active LOW)

Clock Pulse Input

Inputs

3-STATE Outputs

No Connect

FBGA Pin Assignments

1

2

3

4

5

6

A

O0

NC OE1 CP1 NC

I0

B

O2

O1

NC

NC

I1

I2

C

O4

O3

VCC VCC

I3

I4

D

O6

O5 GND GND I5

I6

E

O8

O7 GND GND I7

I8

F

O10

O9 GND GND

I9

I10

G

O12

O11 VCC VCC

I11

I12

H

O14

O13

NC

NC

I13

I14

J

O15 NC OE2 CP2 NC

I15

Truth Tables

Pin Assignment for FBGA

Inputs

CP1

OE1

L

I0–I7

H



L

L

L

L

X

X

H

X

Outputs

O0–O7

H

L

Oo

Z

(Top Thru View)

Functional Description

The LVT16374 and LVTH16374 consist of sixteen

edge-triggered flip-flops with individual D-type inputs and

3-STATE true outputs. The device is byte controlled with

each byte functioning identically, but independent of the

other. The control pins can be shorted together to obtain

full 16-bit operation. Each byte has a buffered clock and

buffered Output Enable common to all flip-flops within that

byte. The description which follows applies to each byte.

Inputs

CP2

OE2

L



L

I8–I15

H

L

L

L

X

X

H

X

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Z = HIGH Impedance

Oo = Previous Oo before HIGH to LOW of CP

Outputs

O8–O15

H

L

Oo

Z

Each flip-flop will store the state of their individual D-type

inputs that meet the setup and hold time requirements on

the LOW-to-HIGH Clock (CPn) transition. With the Output

Enable (OEn) LOW, the contents of the flip-flops are avail-

able at the outputs. When OEn is HIGH, the outputs go to

the high impedance state. Operation of the OEn input does

not affect the state of the flip-flops.

www.fairchildsemi.com

2

Share Link: