74LVT16374(1999) データシートの表示（PDF） - Fairchild Semiconductor

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74LVT16374
(Rev.:1999)

Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs

Fairchild Semiconductor 

Connection Diagram

Pin Descriptions

Pin Names

OEn

CPn

I0–I15

O0–O15

Description

Output Enable Input (Active LOW)

Clock Pulse Input

Inputs

3-STATE Outputs

Truth Tables

Inputs

CP1

OE1

L

I0–I7

H



L

L

L

L

X

X

H

X

Outputs

O0–O7

H

L

Oo

Z

Inputs

CP2

OE2

L



L

I8–I15

H

L

L

L

X

X

H

X

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Z = HIGH Impedance

Oo = Previous Oo before HIGH to LOW of CP

Outputs

O8–O15

H

L

Oo

Z

Functional Description

The LVT16374 and LVTH16374 consist of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true

outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins

can be shorted together to obtain full 16-bit operation. Each byte has a buffered clock and buffered Output Enable common

to all flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their

individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With

the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go

to the high impedance state. Operation of the OEn input does not affect the state of the flip-flops.

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