74LVC3G17 データシートの表示（PDF） - NXP Semiconductors.

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74LVC3G17

Triple non-inverting Schmitt trigger with 5 V tolerant input

NXP Semiconductors. 

NXP Semiconductors

74LVC3G17

Triple non-inverting Schmitt trigger with 5 V tolerant input

7. Pinning information

7.1 Pinning

74LVC3G17

1A 1

3Y 2

2A 3

GND 4

8 VCC

7 1Y

6 3A

5 2Y

001aab106

Fig 4. Pin configuration SOT505-2 (TSSOP8) and

SOT765-1 (VSSOP8)

74LVC3G17

1A 1

8 VCC

3Y 2

7 1Y

2A 3

6 3A

GND 4

5 2Y

001aac023

Transparent top view

Fig 5. Pin configuration SOT833-1 (XSON8)

74LVC3G17

1A 1

3Y 2

8 VCC

7 1Y

2A 3

6 3A

GND 4

5 2Y

001aai246

Transparent top view

Fig 6. Pin configuration SOT996-2 (XSON8U)

terminal 1

index area

74LVC3G17

1Y 1

7 1A

3A 2

6 3Y

2Y 3

5 2A

001aag404

Transparent top view

Fig 7. Pin configuration SOT902-1 (XQFN8U)

74LVC3G17_6

Product data sheet

Rev. 06 — 6 June 2008

© NXP B.V. 2008. All rights reserved.

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