N74F862N(2004) データシートの表示（PDF） - Philips Electronics
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N74F862N Datasheet PDF : 10 Pages
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Philips Semiconductors
Bus transceiver, inverting (3-State)
Product data
74F862
FEATURES
• Provide high performance bus interface buffering for wide
data/address paths or buses carrying parity
• High impedance NPN base inputs for reduced loading (20 µA in
HIGH and LOW states)
• IIL is 20 µA for minimum bus loading
• Buffered control inputs for light loading, or increased fan-in as
required with MOS microprocessors
• Positive and negative over-shoots are clamped to ground
• 3-State outputs glitch free during power-up and power-down
• Slim dual In-line (DIP) 300 mil package
• Broadside pinout
• Outputs sink 64 mA
DESCRIPTION
The 74F862 bus transceiver provides a high performance inverting
bus interface for wide data/address paths of buses carrying parity.
TYPE
74F862
TYPICAL
PROPAGATION
DELAY
6.0 ns
TYPICAL
SUPPLY CURRENT
(TOTAL)
150 mA
ORDERING INFORMATION
COMMERCIAL RANGE: VCC = 5 V ± 10%; Tamb = 0 °C to +70 °C
Type number
Package
Name
Description
Version
N74F862N
DIP24
plastic dual in-line package; 24 leads (300 mil)
SOT222-1
N74F862D (see Note 1)
SO24
plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
NOTE:
1. Thermal mounting techniques are recommended. See SMD Process Applications for a discussion of thermal considerations for surface
mounted devices.
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
A0 – A9
Data transmit inputs
1.0/0.033
B0 – B9
Data receive inputs
1.0/0.033
OEBA
Transmit output enable input
1.0/0.033
OEAB
Receive output enable input
1.0/0.033
NOTE: One (1.0) FAST Unit Load is defined as: 20 µA in the HiGH state and 0.6 mA in the LOW state.
PIN CONFIGURATION
LOAD VALUE
HIGH/LOW
20 µA / 20 µA
20 µA / 20 µA
20 µA / 20 µA
20 µA / 20 µA
OEBA 1
A0 2
A1 3
A2 4
A3 5
A4 6
A5 7
A6 8
A7 9
A8 10
A9 11
GND 12
74F862
TOP VIEW
24 VCC
23 B0
22 B1
21 B2
20 B3
19 B4
18 B5
17 B6
16 B7
15 B8
14 B9
13 OEAB
SF00521
2004 Jan 23
2
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