74F164ASC_Q データシートの表示（PDF） - Fairchild Semiconductor
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74F164ASC_Q Datasheet PDF : 7 Pages
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Unit Loading/Fan Out
Pin Names
A, B
CP
MR
Q0–Q7
Description
Data Inputs
Clock Pulse Input (Active Rising Edge)
Master Reset Input (Active LOW)
Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
Input IIH/IIL
Output IOH/IOL
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−1 mA/20 mA
Functional Description
The 74F164A is an edge-triggered 8-bit shift register with
serial data entry and an output from each of the eight
stages. Data is entered serially through one of two inputs
(A or B); either of these inputs can be used as an active
HIGH Enable for data entry through the other input. An
unused input must be tied HIGH.
Each LOW-to-HIGH transition on the Clock (CP) input
shifts data one place to the right and enters into Q0 the log-
ical AND of the two data inputs (A • B) that existed before
the rising clock edge. A LOW level on the Master Reset
(MR) input overrides all other inputs and clears the register
asynchronously, forcing all Q outputs LOW.
Mode Select Table
Operating
Inputs
Outputs
Mode
MR A B Q0 Q1–Q7
Reset (Clear) L X X L
L-L
Hl
l
L q0–q6
Shift
H l h L q0–q6
H h l L q0–q6
H h h H q0–q6
H(h) = HIGH Voltage Levels
L(l) = LOW Voltage Levels
X = Immaterial
qn = Lower case letters indicate the state of the referenced input or output
one setup time prior to the LOW-to-HIGH clock transition.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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