N74F191N データシートの表示（PDF） - Philips Electronics
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N74F191N Datasheet PDF : 14 Pages
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Philips Semiconductors
Up/Down binary counter with reset and ripple clock
Product specification
74F191
FEATURES
• High speed –125MHz typical fMAX
• Synchronous, reversible counting
• 4-Bit binary
• Asynchronous parallel load capability
• Cascadable without external logic
• Single up/down control input
DESCRIPTION
The 74F191 is a 4-bit binary counter. It contains four edge-triggered
master/slave flip-flops with internal gating and steering logic to
provide asynchronous preset and synchronous count-up and
count-down operations.
Asynchronous parallel load capability permits the counter to be
preset to any desired number. Information present on the parallel
data inputs (D0 - D3) is loaded into the counter and appears on the
outputs when the Parallel Load (PL) input is Low. This operation
overrides the counting function. Counting is inhibited by a High level
on the count enable (CE) input. When CE is Low, internal state
changes are initiated. Overflow/underflow indications are provided
by two types of outputs, the Terminal Count (TC) and Ripple Clock
(RC).
The TC output is normally Low and goes High when: 1) the count
reaches zero in the countdown mode or 2) reaches “15” in the count
up mode. The TC output will remain High until a state change
occurs, either by counting or presetting, or until U/D is changed. TC
output should not be used as a clock signal because it is subject to
decoding spikes. The TC signal is used internally to enable the RC
output. When TC is High and CE is Low, the RC follows the clock
pulse. The RC output essentially duplicates the Low clock pulse
width, although delayed in time by two gate delays.
PIN CONFIGURATION
D1 1
Q1 2
Q0 3
CE 4
U/D 5
Q2 6
Q3 7
GND 8
16 VCC
15 D0
14 CP
13 RC
12 TC
11 PL
10 D2
9 D3
SF00729
TYPE
74F191
TYPICAL fMAX
125MHz
TYPICAL
SUPPLY CURRENT
(TOTAL)
40mA
ORDERING INFORMATION
DESCRIPTION
16-pin plastic DIP
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
N74F191N
16-pin plastic SO
N74F191D
PKG DWG #
SOT38-4
SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
D0 - D3
CE
Data inputs
Count enable input (active Low)
1.0/1.0
1.0/3.0
CP
Clock pulse input (active rising edge)
1.0/1.0
PL
Asynchronous parallel load control input (active Low)
1.0/1.0
U/D
Up/down count control input
1.0/1.0
Q0 - Q3
RC
Flip-flop outputs
Ripple clock output (active low)
50/33
50/33
TC
Terminal count output
50/33
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state.
LOAD VALUE
HIGH/LOW
20µA/0.6mA
20µA/1.8mA
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
1.0mA/20mA
1.0mA/20mA
1.0mA/20mA
1995 Jul 17
2
853–0352 15459
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