74ALVCH16823DGG データシートの表示（PDF） - Philips Electronics

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74ALVCH16823DGG

18-bit bus-interface D-type flip-flop with reset and enable (3-State)

Philips Electronics 

Philips Semiconductors

18-bit D-type flip-flop (3-State)

Product specification

74ALVCH16823

FEATURES

• Wide supply voltage range of 1.2V to 3.6V

• Complies with JEDEC standard no. 8-1A.

• CMOS low power consumption

• Direct interface with TTL levels

• Current drive ± 24 mA at 3.0 V

• Multibyte™flow-through standard pin-out architecture

• Low inductance multiple VCC and GND pins to minimize noise and

ground bounce

• All data inputs have bus hold

• Output drive capability 50Ω transmission lines @ 85°C

DESCRIPTION

The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring

separate D-type inputs for each flip-flop and 3-state outputs for bus

oriented applications. Incorporates bushold data inputs which

eliminate the need for external pull-up resistors to hold unused

inputs. The74ALVCH16823 consists of two sections of nine

edge-triggered flip-flops. A clock (CP) input, an output-enable (OE)

input, a Master reset (MR) input and a clock-enable( CE) input are

provided for each total 9-bit section.

With the clock-enable (CE) input LOW, the D-type flip-flops will store

the state of their individual D-inputs that meet the set-up and hold

time requirements on the LOW-to-HIGH CP transition. Taking CE

HIGH disables the clock buffer, thus latching the outputs. Taking the

Master reset (MR) input LOW causes all the Q outputs to go LOW

independently of the clock.

When OE is LOW, the contents of the flip-flops are available at the

outputs. When the OE is HIGH, the outputs go to the high

impedance OFF-state. Operation of the OE input does not affect the

state of flip-flops.

Active bus hold circuitry is provided to hold unused or floating data

inputs at a valid logic level.

QUICK REFERENCE DATA

GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5ns

SYMBOL

PARAMETER

CONDITIONS

tPHL/tPLH

Fmax

CI

CPD

Propagation delay

CP to Qn

Maximum clock frequency

Input capacitance

Power dissipation capacitance per latch

VCC = 2.5V, CL = 30pF

VCC = 3.3V, CL = 50pF

VCC = 2.5V, CL = 30pF

VCC = 3.3V, CL = 50pF

VI = GND to VCC1

Outputs enabled

Outputs disabled

NOTES:

1. CPD is used to determine the dynamic power dissipation (PD in mW):

PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where:

fi = input frequency in MHz; CL = output load capacity in pF;

fo = output frequency in MHz; VCC = supply voltage in V;

S (CL × VCC2 × fo) = sum of outputs.

TYPICAL

2.1

2.1

300

350

5.0

16

10

UNIT

ns

MHz

pF

pF

ORDERING INFORMATION

PACKAGES

56-Pin Plastic SSOP Type II

56-Pin Plastic TSSOP Type II

TEMPERATURE RANGE OUTSIDE NORTH AMERICA

-40°C to +85°C

74ALVCH16823 DL

-40°C to +85°C

74ALVCH16823 DGG

NORTH AMERICA

ACH16823 DL

ACH16823 DGG

DWG NUMBER

SOT371-1

SOT364-1

1998 Jul 29

2

853–2100 19800

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