Philips Semiconductors
8-bit serial-in/parallel-out shift register
Product specification
74AHC164; 74AHCT164
SYMBOL
PARAMETER
TEST CONDITIONS
WAVEFORMS CL
Tamb (°C)
25
−40 to +85 −40 to +125 UNIT
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VCC = 4.5 to 5.5 V; typical values at VCC = 5.0 V
tPHL/tPLH
tPHL
fmax
propagation delay
CP to Qn
propagation delay
MR to Qn
maximum clock pulse
frequency
see Figs 6 and 9 15 pF − 4.5 9.0
see Figs 7 and 9
− 4.0 8.6
see Figs 6 and 9
125 175 −
1.0 10.5 1.0
1.0 10.0 1.0
105 −
85
tPHL/tPLH propagation delay
CP to Qn
see Figs 6 and 9 50 pF − 6.4 11.0 1.0 12.5 1.0
tPHL
propagation delay
see Figs 7 and 9
MR to Qn
− 5.8 10.6 1.0 12.0 1.0
tW
clock pulse width HIGH see Figs 6 and 9
5.0 − −
5.0 −
5.0
or LOW
master reset pulse
width LOW
see Figs 7 and 9
5.0 − −
5.0 −
5.0
tsu
set-up time
Dsa, Dsb to CP
see Figs 8 and 9
th
hold time
Dsa, Dsb to CP
see Figs 8 and 9
trem
removal time MR to CP see Figs 7 and 9
fmax
maximum clock pulse see Figs 6 and 9
frequency
4.5 − −
4.5 −
4.5
2.0 − −
2.0 −
2.0
2.5 − −
2.5 −
2.5
85 115 −
75 −
65
11.5 ns
11.0 ns
−
MHz
14.0 ns
13.5 ns
−
ns
−
ns
−
ns
−
ns
−
ns
−
MHz
2000 Aug 15
10