73M1903C
Modem Analog Front End
DATA SHEET
AC TIMING
PARAMETER
SCLK Period (Tsclk) (Fs=8kHz)
SCLK to FS Delay (td1)
SCLK to FS Delay (td2)
SCLK to SDOUT Delay (td3) (With 10pf load)
Setup Time SDIN to SCLK (tsu)
Hold Time SDIN to SCLK (th)
MIN
NOM
-
1/2.048MHz
-
-
-
--
-
-
15
-
10
-
Table 14: -Serial interface Timing
MAX
-
20
20
20
-
-
UNIT
ns
ns
ns
ns
ns
ns
td1
td2
tclk
SCLK
FS
SDOUT
SDIN
RX15
td3
tsu
RX14
RX1
RX0
TX15
TX14
TX
TX0
th
Figure 14: Serial Port Data Timing
Page: 31 of 46
© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 4.3