56F805 データシートの表示（PDF） - Freescale Semiconductor
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56F805 Datasheet PDF : 56 Pages
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Part 1 Overview
1.1 56F805 Features
1.1.1 Processing Core
• Efficient 16-bit 56800 family processor engine with dual Harvard architecture
• As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• Two 36-bit accumulators, including extension bits
• 16-bit bidirectional barrel shifter
• Parallel instruction set with unique processor addressing modes
• Hardware DO and REP loops
• Three internal address buses and one external address bus
• Four internal data buses and one external data bus
• Instruction set supports both DSP and controller functions
• Controller style addressing modes and instructions for compact code
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/OnCE debug programming interface
1.1.2 Memory
• Harvard architecture permits as many as three simultaneous accesses to Program and Data memory
• On-chip memory including a low-cost, high-volume Flash solution
— 31.5K × 16 bit words of Program Flash
— 512 × 16-bit words of Program RAM
— 4K× 16-bit words of Data Flash
— 2K × 16-bit words of Data RAM
— 2K × 16-bit words of Boot Flash
• Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states
— As much as 64K × 16 bits of Data memory
— As much as 64K × 16 bits of Program memory
1.1.3 Peripheral Circuits for 56F805
• Two Pulse Width Modulator modules each with six PWM outputs, three Current Sense inputs, and four
Fault inputs, fault tolerant design with dead time insertion; supports both center- and edge-aligned modes
• Two 12-bit Analog-to-Digital Converters (ADC) which support two simultaneous conversions; ADC and
PWM modules can be synchronized
• Two Quadrature Decoders each with four inputs or two additional Quad Timers
56F805 Technical Data, Rev. 15
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Freescale Semiconductor
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