To/From IPBus Bridge
Architecture Block Diagram
OCCS
(ROSC / PLL /
OSC)
GPIO A
GPIO B
GPIO C
GPIO D
Interrupt
Controller
Low-Voltage Interrupt
POR & LVI
System POR
SIM
RESET
(Muxed with GPIOA7)
COP Reset
COP
IPBus
(Continues on Figure 1-3)
Figure 1-2 Peripheral Subsystem
56F8033/56F8023 Data Sheet, Rev. 6
Freescale Semiconductor
11