RAS#
V
V
IH
IL
CASL#/CASH#
V IH
V IL
ADDR
V IH
V IL
WE#
V IH
V IL
DQ
V
V
IOH
IOL
OE# VVIIHL
16Mb: 1 MEG x16
EDO DRAM
EDO-PAGE-MODE READ EARLY WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
tRASP
tRP
tCRP
tCSH
tPC
tPC
tRCD
tCAS, tCLCH
tCP
tCAS, tCLCH
tCP
tRSH
tCAS, tCLCH
tCP
tASR
tRAD
tRAH
ROW
tAR
tASC
tCAH
COLUMN (A)
tRCS
tAA
tRAC
tCAC
OPEN
tOE
tASC
tCAH
COLUMN (B)
tRCH
tCPA
tAA
tCAC
tCOH
VALID DOUT
tWHZ
VALID
DOUT
tASC
tACH
tCAH
COLUMN (N)
tWCS
tWCH
tDS tDH
VALID DIN
ROW
DON’T CARE
UNDEFINED
TIMING PARAMETERS
SYMBOL
tAA
tACH
tAR
tASC
tASR
tCAC
tCAH
tCAS
tCLCH
tCOH
tCP
tCPA
tCRP
tCSH
tDH
-5
MIN
MAX
25
12
38
0
0
13
8
8
10,000
5
3
8
28
5
38
8
-6
MIN
MAX
30
15
45
0
0
15
10
10
10,000
5
3
10
35
5
45
10
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
tDS
tOE
tPC
tRAC
tRAD
tRAH
tRASP
tRCD
tRCH
tRCS
tRP
tRSH
tWCH
tWCS
tWHZ
MIN
0
20
9
9
50
11
0
0
30
13
8
0
0
-5
MAX
12
50
125,000
12
MIN
0
25
12
10
60
14
0
0
40
15
10
0
0
-6
MAX
15
60
125,000
15
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1 Meg x 16 EDO DRAM
D52_B.p65 – Rev. B; Pub. 3/01
18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc