HN58V1001P データシートの表示（PDF） - Hitachi -> Renesas Electronics

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HN58V1001P

1M EEPROM (128-kword × 8-bit) Ready/Busy and RES function

Hitachi -> Renesas Electronics 

Block Diagram

VCC

VSS

RES

OE

CE

WE

RES

A0

to

A6

A7

to

A16

High voltage generator

Control logic and timing

Address

buffer and

latch

Y decoder

X decoder

HN58V1001 Series

I/O0to I/O7 RDY/Busy

I/O buffer

and

input latch

Y gating

Memory array

Data latch

Operation Table

Operation

CE

OE

WE

RES

Read

Standby

VIL

VIL

VIH

VH * 1

VIH

×*2

×

×

Write

VIL

VIH

VIL

VH

Deselect

VIL

VIH

VIH

VH

Write Inhibit

×

×

VIH

×

Data Polling

×

VIL

×

×

VIL

VIL

VIH

VH

Program reset

×

×

×

VIL

Notes: 1. Refer to the recommended DC operating conditions.

2. × : Don’t care

RDY/Busy

High-Z

High-Z

High-Z to VOL

High-Z

—

—

VOL

High-Z

I/O

Dout

High-Z

Din

High-Z

—

—

Dout (I/O7)

High-Z

3

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