AD5622 データシートの表示（PDF） - Analog Devices
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コンポーネント説明
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AD5622 Datasheet PDF : 24 Pages
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Data Sheet
AD5602/AD5612/AD5622
Parameter
t8
t9
t10
t11
t11A
t12
tSP4
Test Conditions/Comments2
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Fast mode
High speed mode
Limit at TMIN, TMAX
Min
Max
4
0.6
160
1000
300
10
80
20
160
300
300
10
80
20
160
1000
300
10
40
20
80
1000
300
10
80
20
160
300
300
10
40
20
80
0
50
0
10
Unit
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
tSU;STO, setup time for a stop condition
tRDA, rise time of SDA signal
tFDA, fall time of SDA signal
tRCL, rise time of SCL signal
tRCL1, rise time of SCL signal after a repeated start
condition and after an acknowledge bit
tFCL, fall time of SCL signal
Pulse width of spike suppressed
1 See Figure 2. High speed mode timing specification applies to the AD5602-1/AD5612-1/AD5622-1 only. Standard and fast mode timing specifications apply to the
AD5602-1/AD5612-1/AD5622-1 and AD5602-2/AD5612-2/AD5622-2.
2 CB refers to the capacitance on the bus line.
3 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior
of the device.
4 Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode or 10 ns for high speed mode.
TIMING DIAGRAM
SCL
SDA
t7
PS
t11
t2
t6
t4
t12
t1
t3
t6
t5
t10
S
Figure 2. 2-Wire Serial Interface Timing Diagram
t8
t9
P
Rev. D | Page 5 of 24
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