53C810 データシートの表示（PDF） - Unspecified

部品番号

コンポーネント説明

メーカー

53C810

PCI-SCSI I/O Processor

Unspecified 

Chapter Four

Signal Descriptions

SCSI Signals

Symbol

Pin No.

Type

SCLK

51

I

SDI (7-0)

SDP

SCTRIJ

66, 67, 69, I/O

70, 71,72

74, 75, 76

55, 56,57

I/O

59, 60, 61

62, 64, 65

PREUMINARY

Description

SCLK is used to derive all SCSI-related timings. The speed of

this clock is determined by the" application's requirements; in

some applications SCLK may be sourced internally

from the PCI bus clock (CLK). IfSCLK is internally sourced,

then the SCLK pin should be tied low.

SCSI Data includes the following data lines and parity signals:

SD7-0 (8-bit SCSI data bus), SDP(SCSI data parity bit).

SCSI Control includes the following signals:

CD SCSI phase line, command/data

I 01 SCSI phase line, input/output

MSGI SCSI phase line, message

REQI Data handshake signal from target device

ACKJ Data handshake signal from initiator device

BSY SCSI bus arbitration signal, busy

A1N1 Attention, the initiator is requesting a

message-out phase

RSTI SCSI bus reset.

4-6

Share Link: